DS90CF366 Datasheet, PDF (3/20 Pages) Texas Instruments – 20 to 85 MHz Shift Clock Support, Rx Power Consumption <142 mW (typ) @85MHz Grayscale

DS90CF366, DS90CF386
www.ti.com
SNLS055I – NOVEMBER 1999 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified⁽¹⁾
Symbol
Parameter
Conditions
Min Typ Max Units
RECEIVER SUPPLY CURRENT
ICCRW Receiver Supply Current Worst Case
C_L = 8 pF, Worst Case
Pattern,
DS90CF386 Figure 3,
Figure 6
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
49 70
mA
53 75
mA
81 114 mA
f = 85 MHz
96 135 mA
ICCRW Receiver Supply Current Worst Case
C_L = 8 pF, Worst Case
Pattern,
DS90CF366 Figure 3,
Figure 6
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
49 60
mA
53 65
mA
78 100 mA
f = 85 MHz
90 115 mA
ICCRG Receiver Supply Current, 16 Grayscale
C_L = 8 pF, 16 Grayscale
Pattern, Figure 4, Figure 5,
Figure 6
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
28 45
mA
30 47
mA
43 60
mA
ICCRZ Receiver Supply Current Power Down⁽²⁾
f = 85 MHz
Power Down = Low Receiver Outputs Stay Low
during Power Down Mode
43 70
mA
140 400
μA
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except V_OD and ΔV _OD).
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified⁽¹⁾
Symbol
Parameter
Min
CLHT
CMOS/TTL Low-to-High Transition Time Figure 6
CHLT
CMOS/TTL High-to-Low Transition Time Figure 6
RSPos0 Receiver Input Strobe Position for Bit 0 Figure 13,
f = 85 MHz
0.49
Figure 14
RSPos1 Receiver Input Strobe Position for Bit 1
2.17
RSPos2 Receiver Input Strobe Position for Bit 2
3.85
RSPos3 Receiver Input Strobe Position for Bit 3
5.53
RSPos4 Receiver Input Strobe Position for Bit 4
7.21
RSPos5 Receiver Input Strobe Position for Bit 5
8.89
RSPos6
RSKM
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin⁽²⁾ Figure 15
f = 85 MHz
10.57
290
RCOP
RxCLK OUT Period Figure 7
11.76
RCOH
RxCLK OUT High Time Figure 7
f = 85 MHz
4.5
RCOL
RxCLK OUT Low Time Figure 7
4.0
RSRC
RxOUT Setup to RxCLK OUT Figure 7
2.0
RHRC
RxOUT Hold to RxCLK OUT Figure 7
3.5
RCCD
RxCLK IN to RxCLK OUT Delay @ 25°C, V_CC = 3.3V Figure 8
5.5
RPLLS
Receiver Phase Lock Loop Set Figure 9
RPDD
Receiver Power Down Delay Figure 12
Typ ⁽¹⁾
2.0
1.8
0.84
2.52
4.20
5.88
7.56
9.24
10.92
T
5
5
7.0
Max
3.5
3.5
1.19
2.87
4.55
6.23
7.91
9.59
11.27
50
7
6.5
9.5
10
1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ms
μs
(1) Typical values are given for V_CC = 3.3V and T_A = +25C.
(2) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows
for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 150 ps).
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