DRV8402 Datasheet, PDF (9/18 Pages) Texas Instruments – Dual Full Bridge PWM Motor Driver

DRV8402
www.ti.com ........................................................................................................................................................................................... SLES222 – DECEMBER 2008
THEORY OF OPERATION
POWER SUPPLIES
To help with system design, the DRV8402 needs only
a 12 V supply in addition to power-stage supply. An
internal voltage regulator provides suitable voltage
levels for the digital and low-voltage analog circuitry.
Additionally, all circuitry requiring a floating voltage
supply, for example, the high-side gate drive, is
accommodated by built-in bootstrap circuitry requiring
only a few external capacitors.
To provide electrical characteristics, the PWM signal
path including gate drive and output stage is
designed as identical, independent half-bridges. For
this reason, each half-bridge has separate gate drive
supply (GVDD_X), bootstrap pins (BST_X), and
power-stage supply pins (PVDD_X). Furthermore, an
additional pin (VDD) is provided as supply for all
common circuits. Although supplied from the same
12-V source, it is recommended that a 1 – 10 Ω
resistor is used to separate the GVDD_X pins from
VDD on the printed-circuit board (PCB). Special
attention should be paid to placing all decoupling
capacitors as close to their associated pins as
possible. In general, inductance between the power
supply pins and decoupling capacitors must be
avoided.
For a properly functioning bootstrap circuit, a small
ceramic capacitor must be connected from each
bootstrap pin (BST_X) to the power-stage output pin
(OUT_X). When the power-stage output is low, the
bootstrap capacitor is charged through an internal
diode connected between the gate-drive
power-supply pin (GVDD_X) and the bootstrap pin.
When the power-stage output is high, the bootstrap
capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply
for the high-side gate driver. In an application with
PWM switching frequencies in the range from 25 kHz
to 500 kHz, the use of 47 nF ceramic capacitors, size
0603 or 0805, is recommended for the bootstrap
supply. These 47 nF capacitors ensure sufficient
energy storage, even during minimal PWM duty
cycles, to keep the high-side power stage FET fully
turned on during the remaining part of the PWM
cycle. In an application running at a switching
frequency lower than 25 kHz, the bootstrap capacitor
might need to be increased in value.
compliance, and system reliability, it is important that
each PVDD_X pin is decoupled with a ceramic
capacitor placed as close as possible to each supply
pin. It is recommended to follow the PCB layout of
the DRV8402 in EVM board.
The 12 V supply should be from a low-noise,
low-output-impedance voltage regulator. Likewise, the
50 V power-stage supply is assumed to have low
output impedance and low noise. The power-supply
sequence is not critical as facilitated by the internal
power-on-reset circuit. Moreover, the DRV8402 is
fully protected against erroneous power-stage turn-on
due to parasitic gate charging. Thus, voltage-supply
ramp rates (dv/dt) are non-critical within the specified
range (see the Recommended Operating Conditions
section of this data sheet).
SYSTEM POWER-UP/POWER-DOWN
SEQUENCE
Powering Up
The DRV8402 does not require a power-up
sequence. The outputs of the H-bridges remain in a
highimpedance state until the gate-drive supply
voltage (GVDD_X) and VDD voltage are above the
undervoltage protection (UVP) voltage threshold (see
the Electrical Characteristics section of this data
sheet). Although not specifically required, holding
RESET_AB and RESET_CD in a low state while
powering up the device is recommended. This allows
an internal circuit to charge the external bootstrap
capacitors by enabling a weak pulldown of the
half-bridge output (except in half-bridge modes).
Powering Down
The DRV8402 does not require a power-down
sequence. The device remains fully operational as
long as the gate-drive supply (GVDD_X) voltage and
VDD voltage are above the UVP voltage threshold
(see the Electrical Characteristics section of this data
sheet). Although not specifically required, it is a good
practice to hold RESET_AB and RESET_CD low
during power down to prevent any unknown state
during this transition.
Special attention should be paid to the power-stage
power supply; this includes component selection,
PCB placement, and routing. As indicated, each
half-bridge has independent power-stage supply pins
(PVDD_X). For optimal electrical performance, EMI
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