DRV8402 Datasheet, PDF(10/18 Page) Texas Instruments – Dual Full Bridge PWM Motor Driver

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DRV8402

SLES222 â DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

ERROR REPORTING

The FAULT and OTW pins are both active-low,

open-drain outputs. Their function is for

protection-mode signaling to a PWM controller or

other system-control device.

Any fault resulting in device shutdown is signaled by

the FAULT pin going low. Likewise, OTW goes low

when the device junction temperature exceeds 125Â°C

(see Table 1).

FAULT

OTW

Table 1.

DESCRIPTION

Overtemperature warning and

(overtemperature shut down or

overcurrent shut down or undervoltage

protection) occurred

Overcurrent shut-down or undervoltage

protection occurred

Overtemperature warning

Device under normal operation

Note that asserting either RESET_AB or RESET_CD

low forces the FAULT signal high, independent of

faults being present. For proper error reporting, set

both RESET_AB and RESET_CD high during normal

operation.

TI recommends monitoring the OTW signal using the

system microcontroller and responding to an OTW

signal by reducing the load current to prevent further

heating of the device resulting in device

overtemperature shutdown (OTSD).

To reduce external component count, an internal

pullup resistor to 3.3 V is provided on both FAULT

and OTW outputs. Level compliance for 5-V logic can

be obtained by adding external pull-up resistors to

5 V (see the Electrical Characteristics section of this

data sheet for further specifications).

DEVICE PROTECTION SYSTEM

The DRV8402 contains advanced protection circuitry

carefully designed to facilitate system integration and

ease of use, as well as to safeguard the device from

permanent failure due to a wide range of fault

conditions such as short circuits, overcurrent,

overtemperature, and undervoltage. The DRV8402

responds to a fault by immediately setting the power

stage in a high-impedance (Hi-Z) state and asserting

the FAULT pin low. In situations other than

overcurrent or overtemperature, the device

automatically recovers when the fault condition has

been removed or the gate supply voltage has

increased. For highest possible reliability, recovering

from an overcurrent shut down (OCSD) or OTSD fault

requires external reset of the device (see the Device

Reset section of this data sheet) no sooner than

1 second after the shutdown.

Bootstrap Capacitor Under Voltage Protection

When the device runs at a low switching frequency

(e.g. less than 20 kHz with 47 nF bootstrap

capacitor), the bootstrap capacitor voltage might not

be able to maintain a proper voltage level for the

high-side gate driver. A bootstrap capacitor

undervoltage protection circuit (BST_UVP) will start

under this circumstance to prevent the potential

failure of the high-side MOSFET. When the voltage

on the bootstrap capacitors is less than required for

safe operation, the DRV8402 will initiate bootstrap

capacitor recharge sequences (turn off high side FET

for a short period) until the bootstrap capacitors are

properly charged for safe operation. This function

may also be activated when PWM duty cycle is too

high (e.g. higher than 99.5%). Note that bootstrap

capacitor might not be able to be charged up if no

load is presented at output.

Because the extra pulse width to charge bootstrap

capacitor is so short, that the output current

disruption due to the extra charge is negligible most

of the time when output inductor is present.

Overcurrent (OC) Protection

The device has independent, fast-reacting current

detectors with programmable trip threshold (OC

threshold) on all high-side and low-side power-stage

FETs. There are two settings for OC protection

through Mode selection pins: cycle-by-cycle (CBC)

current limiting mode and OC latching (OCL) shut

down mode.

In CBC current limiting mode, the detector outputs

are monitored by two protection systems. The first

protection system controls the power stage in order to

prevent the output current from further increasing,

i.e., it performs a CBC current-limiting function rather

than prematurely shutting down the device. This

feature could effectively limit the inrush current during

motor start-up or transient without damaging the

device. During short to power and short to ground

condition, the current limit circuitry might not be able

to control the current in a proper level, a second

protection system triggers a latching shutdown,

resulting in the power stage being set in the

high-impedance (Hi-Z) state. Current limiting and

overcurrent protection are independent for

half-bridges A, B, C, and, D, respectively.

In OCL shut down mode, the cycle-by-cycle current

limit and error recovery circuitry is disabled and an

overcurrent condition will cause the device to

shutdown immediately. After shutdown, RESET_AB

and/or RESET_CD must be asserted to restore

normal operation after the overcurrent condition is

removed.

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