DRV8402 Datasheet, PDF (11/18 Pages) Texas Instruments – Dual Full Bridge PWM Motor Driver

DRV8402
www.ti.com ........................................................................................................................................................................................... SLES222 – DECEMBER 2008
For added flexibility, the OC threshold is
programmable within a limited range using a single
external resistor connected between the OC_ADJ pin
and AGND pin. See Table 2 for information on the
correlation between programming-resistor value and
the OC threshold. It should be noted that a properly
functioning overcurrent detector assumes the
presence of a proper inductor at the power-stage
output (minimum 2 µH). Short-circuit protection is not
provided directly at the output pins of the power
stage, but only after the inductor. If a further smaller
inductor is preferred for any reason, using OCL mode
setting is recommended.
Table 2.
OC-Adjust Resistor Values
(kΩ)
22⁽¹⁾
24⁽¹⁾
Max. Current Before OC Occurs
(A)
12.2
11.5
27
10.6
30
9.9
33
9.3
36
8.7
39
8.2
(1) Recommended to use in OCL Mode Only
Overtemperature Protection
The DRV8402 has a two-level temperature-protection
system that asserts an active-low warning signal
(OTW) when the device junction temperature
exceeds 125°C (nominal) and, if the device junction
temperature exceeds 150°C (nominal), the device is
put into thermal shutdown, resulting in all half-bridge
outputs being set in the high-impedance (Hi-Z) state
and FAULT being asserted low. OTSD is latched in
this case and RESET_AB and RESET_CD must be
asserted low.
Undervoltage Protection (UVP) and Power-On
Reset (POR)
The UVP and POR circuits of the DRV8402 fully
protect the device in any power-up/down and
brownout situation. While powering up, the POR
circuit resets the overcurrent circuit and ensures that
all circuits are fully operational when the GVDD_X
and VDD supply voltages reach 9.8 V (typical).
Although GVDD_X and VDD are independently
monitored, a supply voltage drop below the UVP
threshold on any VDD or GVDD_X pin results in all
half-bridge outputs immediately being set in the
high-impedance (Hi-Z) state and FAULT being
asserted low. The device automatically resumes
operation when all supply voltage on the bootstrap
capacitors have increased above the UVP threshold.
DEVICE RESET
Two reset pins are provided for independent control
of half-bridges A/B and C/D. When RESET_AB is
asserted low, all four power-stage FETs in
half-bridges A and B are forced into a
high-impedance (Hi-Z) state. Likewise, asserting
RESET_CD low forces all four power-stage FETs in
half-bridges C and D into a high-impedance state.
In full bridge and parallel full bridge configurations, to
accommodate bootstrap charging prior to switching
start, asserting the reset inputs low enables weak
pulldown of the half-bridge outputs. In half bridge
configuration, the weak pulldowns are not enabled,
and it is, therefore, recommended to precharge
bootstrap capacitor by providing a low pulse on the
PWM inputs first when reset is asserted high.
Asserting either reset input low removes any fault
information to be signaled on the FAULT output, i.e.,
FAULT is forced high.
A rising-edge transition on either reset input allows
the device to resume operation after an overcurrent
fault.
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV8402
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