DRV8402 Datasheet, PDF (6/18 Pages) Texas Instruments – Dual Full Bridge PWM Motor Driver

DRV8402
SLES222 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS
Ta = 25 °C, PVDD = 50 V, GVDD = VDD = 12 V, F_Sw = 400 kHz, unless otherwise noted. All performance is in accordance
with recommended operating conditions unless otherwise specified.
PARAMETER
TEST CONDITIONS
Internal Voltage Regulator and Current Consumption
V_REG
Voltage regulator, only used as a
reference node
VDD = 12 V
I_VDD
I_{GVDD_X}
I_{PVDD_X}
Output Stage
VDD supply current
Gate supply current per half-bridge
Half-bridge X (A, B, C, or D) idle current
Idle, reset mode
Reset mode
Reset mode
R_DS(on)
MOSFET drain-to-source resistance, low T_J = 25°C, includes metallization resistance,
side (LS)
GVDD = 12 V
MOSFET drain-to-source resistance, high T_J = 25°C, includes metallization resistance,
side (HS)
GVDD = 12 V
V_F
t_R
t_F
t_{PD_ON}
t_{PD_OFF}
t_DT
I/O Protection
Diode forward voltage drop
Output rise time
Output fall time
Propagation delay when FET is on
Propagation delay when FET is off
Dead time between HS and LS FETs
T_J = 25°C - 125°C, I_O = 5 A
Resistive load, I_O = 5 A
Resistive load, I_O = 5 A
Resistive load, I_O = 5 A
Resistive load, I_O = 5 A
Resistive load, I_O = 5 A
V_uvp,G
Gate supply voltage GVDD_X
undervoltage protection
V_uvp,hyst ⁽¹⁾
OTW ⁽¹⁾
Hysteresis for gate supply undervoltage
event
Overtemperature warning
OTW_hyst ⁽¹⁾
Hysteresis temperature to reset OTW
event
OTSD ⁽¹⁾
Overtemperature shut down
OTE-OTW_differential ⁽¹⁾
OTE-OTW overtemperature detect
temperature difference
OTSD_HYST ⁽¹⁾
Hysteresis temperature for FAULT to be
released following an OTSD event.
I_OC
Overcurrent limit protection
Resistor—programmable, nominal, R_OCP = 27 kΩ
I_OCT
Overcurrent response time
Time from application of short condition to Hi-Z of
affected FET(s)
R_PD
Internal pulldown resistor at the output of
each half-bridge
Connected when RESET_AB or RESET_CD is
active to provide bootstrap capacitor charge. Not
used in SE mode
Static Digital Specifications
V_IH
V_IL
l_lkg
OTW / FAULT
High-level input voltage
Low-level input voltage
Input leakage current
PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3,
RESET_AB, RESET_CD
R_{INT_PU}
Internal pullup resistance, OTW to
VREG, FAULT to VREG
Internal pullup resistor only
V_OH
High-level output voltage
External pullup of 4.7 kΩ to 5 V
V_OL
Low-level output voltage
I_O = 4 mA
MIN TYP MAX UNIT
2.95
3.3 3.65
V
9
12 mA
1.7
2 mA
0.5
1 mA
90
mΩ
90
mΩ
1
V
9
nS
9
nS
42
nS
40
nS
5
nS
8.5
0.8
115
125
25
150
25
25
10.6
250
V
V
135 °C
°C
°C
°C
°C
A
ns
1
kΩ
2
-100
V
0.8
V
100 µA
20
26
35 kΩ
2.95
3.3 3.65
V
4.5
5
0.2
0.4
V
(1) Specified by design
6
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