DRV8402 Datasheet, PDF (3/18 Pages) Texas Instruments – Dual Full Bridge PWM Motor Driver

DRV8402
www.ti.com ........................................................................................................................................................................................... SLES222 – DECEMBER 2008
DEVICE INFORMATION
Pin Assignment
The DRV8402 is available in a thermally enhanced package:
• 36-pin PSOP3 package (DKD)
This package contains a heat slug that is located on the top side of the device for convenient thermal coupling to
the heatsink.
DKD PACKAGE
(TOP VIEW)
GVDD_B
1
OTW
2
FAULT
3
PWM_A
4
RESET_AB
5
PWM_B
6
OC_ADJ
7
GND
8
AGND
9
VREG
10
M3
11
M2
12
M1
13
PWM_C
14
RESET_CD
15
PWM_D
16
VDD
17
GVDD_C
18
36
GVDD_A
35
BST_A
34
PVDD_A
33
OUT_A
32
GND_A
31
GND_B
30
OUT_B
29
PVDD_B
28
BST_B
27
BST_C
26
PVDD_C
25
OUT_C
24
GND_C
23
GND_D
22
OUT_D
21
PVDD_D
20
BST_D
19
GVDD_D
MODE Selection Pins
MODE PINS
M3
M2
M1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
OUTPUT
CONFIGURATION
2 FB
2 FB
1 PFB
1 PFB
4 HB
4 HB
DESCRIPTION
Dual full bridge with cycle-by-cycle current limit
Dual full bridge with OC latching shutdown (no cycle-by-cycle current limit)
Parallel full bridge with cycle-by-cycle current limit
Parallel full bridge with OC latching shutdown
Half bridge with cycle-by-cycle current limit. Protection works similarly to full
bridge mode. Only difference in half bridge mode is that OUT_X is Hi-Z
instead of a pulldown through internal pulldown resistor when RESET pin is
low.
Half bridge with OC latching shutdown. Protection works similarly to full
bridge mode. Only difference in half bridge mode is that OUT_X is Hi-Z
instead of a pulldown through internal pulldown resistor when RESET pin is
low.
Reserved
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): DRV8402
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