BQ34Z653 Datasheet, PDF (9/25 Pages) Texas Instruments – SBS 1.1-Compliant Gas Gauge and Protection Enabled with Impedance Track with External Battery Heater Control and LCD Display

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SLUSB53 – JULY 2012
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range (unless otherwise noted), T_A = –40°C to 85°C, V_(REG25) = 2.41 V to 2.59 V,
V_(BAT) = 14 V, C_(REG25) = 1 µF, C_(REG33) = 2.2 µF; typical values at T_A = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R_DS(on)
TOUT pass element resistance
LED OR LCD OUTPUTS
I_(TOUT) = 1 mA; R_DS(on) = (V_(REG25) –
V_(TOUT) )/ 1 mA; T_A = –40°C to 100°C
50
100
Ω
V_OL
Output low voltage
VCELL+ HIGH VOLTAGE TRANSLATION
LED1, LED2, LED3, LED4, LED5
0.4
V
V_(VCELL+OUT)
V_(VCELL+REF) Translation output
V_(VCELL+PACK)
V_(VCELL+BAT)
CMMR
Common mode rejection ratio
VC(n) – VC(n+1) = 0 V;
T_A = –40°C to 100°C
VC(n) – VC(n+1) = 4.5 V;
T_A = –40°C to 100°C
Internal AFE reference voltage;
T_A = –40°C to 100°C
Voltage at PACK pin;
T_A = –40°C to 100°C
Voltage at BAT pin;
T_A = –40°C to 100°C
VCELL+
0.950
0.975
1
0.275
0.3
0.375
0.965
0.975
0.985
V
0.98 ×
V_(PACK)/18
V_(PACK)/18
1.02 ×
V_(PACK)/18
0.98 ×
V_(BAT)/18
V_(BAT)/18
1.02 ×
V_(BAT)/18
40
dB
K
Cell scale factor
K= {VCELL+ output (VC5=0 V; VC4=4.5
V) – VCELL+ output (VC5 = 0 V; VC4 =0
V)}/4.5
K= {VCELL+ output (VC2 = 13.5 V; VC1
= 18 V) – VCELL+ output
(VC5 = 13.5 V; VC1 = 13.5 V)}/4.5
0.147
0.147
0.150
0.150
0.153
0.153
I_(VCELL+OUT)
Drive Current to VCELL+ capacitor
VC(n) – VC(n+1) = 0 V; VCELL+ = 0 V;
T_A = –40°C to 100°C
12
18
V_(VCELL+O)
CELL offset error
CELL output (VC2 = VC1 = 18 V) – CELL
output (VC2 = VC1 = 0 V)
–18
–1
μA
18
mV
I_VCnL
VC(n) pin leakage current
CELL BALANCING
VC1, VC2, VC3, VC4, VC5 = 3 V
–1
0.01
1
μA
R_BAL
Internal cell balancing FET resistance
R_DS(on) for internal FET switch at
V_DS = 2 V; T_A = 25°C
200
400
600
Ω
HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; T_A = 25°C (unless otherwise noted)
V_(OL)
OL detection threshold voltage
accuracy
V_OL = 25 mV (min)
V_OL = 100 mV; RSNS = 0, 1
V_OL = 205 mV (max)
15
25
90
100
185
205
35
110
mV
225
V_(SCC)
SCC detection threshold voltage
accuracy
V_(SCC) = 50 mV (min)
V_(SCC) = 200 mV; RSNS = 0, 1
V_(SCC) = 475 mV (max)
30
50
180
200
428
475
70
220
mV
523
V_(SCD)
SCD detection threshold voltage
accuracy
V_(SCD) = –50 mV (min)
V_(SCD) = –200 mV; RSNS = 0, 1
V_(SCD) = –475 mV (max)
–30
–50
–70
–180
–200
–220
mV
–428
–475
–523
t_da
Delay time accuracy
±15.25
μs
t_pd
Protection circuit propagation delay
50
μs
FET DRIVE CIRCUIT; T_A = 25°C (unless otherwise noted)
V_(DSGON)
DSG pin output on voltage
V_(DSGON) = V_(DSG) – V_(PACK);
V_(GS) = 10 MΩ; DSG and CHG on;
T_A = –40°C to 100°C
8
12
16
V
V_(CHGON)
CHG pin output on voltage
V_(CHGON) = V_(CHG) – V_(BAT);
V_(GS) = 10 MΩ; DSG and CHG on;
T_A = –40°C to 100°C
8
12
16
V
V_(DSGOFF)
DSG pin output off voltage
V_(DSGOFF) = V_(DSG) – V_(PACK)
0.2
V
V_(CHGOFF)
CHG pin output off voltage
V_(CHGOFF) = V_(CHG) –V_(BAT)
0.2
V
t_r
Rise time
C_L= 4700 pF; V_(PACK) ≤ DSG ≤ V_(PACK) +
4V
C_L= 4700 pF; V_(BAT) ≤ CHG ≤ V_(BAT) + 4 V
400
1000
μs
400
1000
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