BQ34Z653 Datasheet, PDF (5/25 Pages) Texas Instruments – SBS 1.1-Compliant Gas Gauge and Protection Enabled with Impedance Track with External Battery Heater Control and LCD Display

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PACKAGE PINOUT DIAGRAM
SLUSB53 – JULY 2012
DBT PACKAGE
(TOP VIEW)
DSG 1
PACK 2
VCC 3
ZVCHG 4
GPOD 5
PMS 6
VSS 7
REG33 8
TOUT 9
VCELL+ 10
ALERT 11
COM 12
TS1 13
TS2 14
PRES 15
PFIN 16
SAFE 17
SMBD 18
NC 19
SMBC 20
DISP 21
VSS 22
44 CHG
43 BAT
42 VC1
41 VC2
40 VC3
39 VC4
38 VC5
37 ASRP
36 ASRN
35 RESET
34 VSS
33 RBI
32 REG25
31 VSS
30 MRST
29 GSRN
28 GSRP
27 LED5/SEG5
26 LED4/SEG4
25 LED3/SEG3
24 LED2/SEG2
23 LED1/SEG1
PIN
NO.
NAME
1
DSG
2
PACK
3
VCC
4
ZVCHG
5
GPOD
6
PMS
7
VSS
8
REG33
9
TOUT
10
VCELL+
11
ALERT
12
COM
PIN FUNCTIONS
I/O ⁽¹⁾
DESCRIPTION
O
IA, P
P
O
OD
I
P
P
P
—
I/OD
O
High-side N-channel discharge FET gate drive
Battery pack input voltage sense input. It also serves as device wake up when device is in SHUTDOWN
mode.
Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to ensure
device supply either from battery stack or battery pack input.
P-channel pre-charge FET gate drive
High voltage general purpose open drain output. It can be configured to be used in pre-charge condition.
PRE-CHARGE mode setting input. Connect to PACK to enable 0v pre-charge using charge FET
connected at CHG pin. Connect to VSS to disable 0-V pre-charge using charge FET connected at CHG
pin.
Negative supply voltage input. Connect all VSS pins together for operation of device.
3.3-V regulator output. Connect at least a 2.2-μF capacitor to REG33 and VSS.
Thermistor bias supply output
Internal cell voltage multiplexer and amplifier output. Connect a 0.1-μF capacitor to VCELL+ and VSS.
Alert output. In case of short circuit condition, overload condition and watchdog timeout, this pin will be
triggered.
Output/open drain: LCD common connection
(1) I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power
Copyright © 2012, Texas Instruments Incorporated
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