BQ34Z653 Datasheet, PDF (13/25 Pages) Texas Instruments – SBS 1.1-Compliant Gas Gauge and Protection Enabled with Impedance Track with External Battery Heater Control and LCD Display

bq34z653
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SLUSB53 – JULY 2012
SMBus TIMING CHARACTERISTICS (continued)
T_A = –40°C to 85°C Typical Values at T_A = 25°C and V_REG25 = 2.5 V (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
t_(SU:DAT)
Data setup time (See Figure 3.)
t_(TIMEOUT) Error signal/detect (See Figure 3.)
t_(LOW)
Clock low period (See Figure 3.)
t_(HIGH)
Clock high period (See Figure 3.)
t_(LOW:SEXT) Cumulative clock low slave extend time
t_(LOW:MEXT)
Cumulative clock low master extend time
(See Figure 3.)
t_f
Clock/data fall time
t_r
Clock/data rise time
See ⁽¹⁾
See ⁽²⁾
See ⁽³⁾
See ⁽⁴⁾
See ⁽⁵⁾
See ⁽⁶⁾
250
ns
25
35
µs
4.7
µs
4
50
µs
25
ms
10
ms
300
ns
1000
ns
(1) The bq34z653 times out when any clock low exceeds t_(TIMEOUT).
(2) t_(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq34z653 that is
in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
(3) t_(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) t_(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Rise time t_r = VILMAX – 0.15) to (VIHMIN + 0.15)
(6) Fall time t_f = 0.9V_DD to (VILMAX – 0.15)
t_SU(STO)
SMBC
t_R
t_BUF
t_F
t_HD(STA)
SMBC
t_F
t_R
t_HIGH
t_LOW
SMBD
P
S
Start and Stop condition
SMBD
SMBC
t_TIMEOUT
SMBC
t_HD(DAT)
t_SU(DAT)
Wait and Hold condition
t_SU(STA)
SMBD
SMBD
Timeout condition
A. SCLKACK is the acknowledge-related clock pulse generated by the master.
Figure 3. SMBus Timing Diagram
S
Repeated Start condition
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