TMS320C6711 Datasheet, PDF (84/129 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS088L − FEBRUARY 1999 − REVISED MAY 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
switching characteristics over recommended operating conditions for synchronous DRAM
cycles^†‡ (see Figure 34−Figure 40) [C6711]
NO.
1
t_d(EKOH-CEV)
2
t_d(EKOH-BEV)
3
t_d(EKOH-BEIV)
4
t_d(EKOH-EAV)
5
t_d(EKOH-EAIV)
8
t_d(EKOH-CASV)
9
t_d(EKOH-EDV)
10 t_d(EKOH-EDIV)
11 t_d(EKOH-WEV)
12 t_d(EKOH-RAS)
PARAMETER
Delay time, ECLKOUT high to CEx valid
Delay time, ECLKOUT high to BEx valid
Delay time, ECLKOUT high to BEx invalid
Delay time, ECLKOUT high to EAx valid
Delay time, ECLKOUT high to EAx invalid
Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid
Delay time, ECLKOUT high to EDx valid
Delay time, ECLKOUT high to EDx invalid
Delay time, ECLKOUT high to AWE/SDWE/SSWE valid
Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid
C6711-100
MIN MAX
1.5
11
11
1.5
11
1.5
1.5
11
11
1.5
1.5
11
1.5
11
C6711-150
MIN MAX
1.5 6.9
6.9
1.5
6.9
1.5
1.5 6.9
7.1
1.5
1.5 6.9
1.5 6.9
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
switching characteristics over recommended operating conditions for synchronous DRAM
cycles^†‡ (see Figure 34−Figure 40) [C6711B]
NO.
PARAMETER
C6711B-100
C6711BGFNA-100
C6711B-150
UNIT
MIN MAX
MIN
MAX
1
t_d(EKOH-CEV)
2
t_d(EKOH-BEV)
3
t_d(EKOH-BEIV)
4
t_d(EKOH-EAV)
5
t_d(EKOH-EAIV)
8
t_d(EKOH-CASV)
9
t_d(EKOH-EDV)
10 t_d(EKOH-EDIV)
11 t_d(EKOH-WEV)
12 t_d(EKOH-RAS)
Delay time, ECLKOUT high to CEx valid
Delay time, ECLKOUT high to BEx valid
Delay time, ECLKOUT high to BEx invalid
Delay time, ECLKOUT high to EAx valid
Delay time, ECLKOUT high to EAx invalid
Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid
Delay time, ECLKOUT high to EDx valid
Delay time, ECLKOUT high to EDx invalid
Delay time, ECLKOUT high to AWE/SDWE/SSWE valid
Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid
1
11
1
8 ns
11
8 ns
1
1
ns
11
8 ns
1
1
ns
1
11
1
8 ns
11
8 ns
1
1
ns
1
11
1
8 ns
1
11
1
8 ns
† _{The C6711/11B/11C/11D SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word}
bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
‡ _{ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM}
accesses.
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