TMS320C6711 Datasheet, PDF (23/129 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS088L − FEBRUARY 1999 − REVISED MAY 2004
SIGNAL
NAME
CLKIN
CLKOUT1
PIN NO.
GFN GDP
A3
A3
D7
—
TYPE^†
I
O
Terminal Functions
IPD/
IPU^‡
IPD
IPD
DESCRIPTION
CLOCK/PLL
Clock Input
Clock output at device speed [C6711/11B only]
The CLK1EN bit in the EMIF GBLCTL register controls the CLKOUT1 pin.
CLK1EN = 0: CLKOUT1 is disabled
CLK1EN = 1: CLKOUT1 enabled to clock [default]
Clock output at half of device speed [C6711/11B only]
CLKOUT2
(/GP0[2])
CLKOUT3
For the C6711C/11D devices, the CLKOUT2 pin is multiplexed with the GP[2] pin.
Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal from the
Y12
Y12
O/Z
IPD ^{clock generator) or this pin can be programmed as GP[2] (I/O/Z).}
When the CLKOUT2 pin is enabled, the CLK2EN bit in the EMIF global control
register (GBLCTL) controls the CLKOUT2 pin (All devices).
CLK2EN = 0: CLKOUT2 is disabled
CLK2EN = 1: CLKOUT2 enabled to clock [default]
—
D10
O
IPD Clock output programmable by OSCDIV1 register in the PLL controller. [11C/11D]
Clock mode select [C6711/11B]
0 − Bypass mode (x1). CPU clock = CLKIN
1 − PLL mode (x4). CPU clock = 4 x CLKIN [default]
CLKMODE0
C4
C4
I
IPU Clock generator input clock source select [C6711C/C6711D]
0 − Reserved. Do not use.
1 − CLKIN square wave [default]
For proper C6711C/11D device operation, this pin must be either left unconnected or
externally pulled up with a 1-kΩ resistor.
PLLV^§
PLLG^§
A4
—
A^¶
C6
—
A^¶
PLL analog V_CC connection for the low-pass filter [C6711/11B only]
PLL analog GND connection for the low-pass filter [C6711/11B only]
PLLF
B5
—
A^¶
PLL low-pass filter connection to external components and a bypass capacitor
[C6711/11B only]
PLLHV
—
C5
A^¶
Analog power (3.3 V) for PLL [C6711C/C6711D only]
JTAG EMULATION
TMS
B7
B7
I
IPU JTAG test-port mode select
TDO
A8
A8
O/Z
IPU JTAG test-port data out
TDI
A7
A7
I
IPU JTAG test-port data in
TCK
A6
A6
I
IPU JTAG test-port clock
TRST
B6
B6
I
IPD
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1
JTAG Compatibility Statement section of this data sheet.
EMU5
B12
B12 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected.
EMU4
C11
C11 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected.
EMU3
B10
B10 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected.
EMU2
D10
D3
I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected.
† _{I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground}
‡ _{For C6711/11B, IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal}
to the opposite supply rail, a 1-kΩ resistor should be used.)
For C6711C/11D, IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-kΩ resistor (approximate) for the IPD
or 18-kΩ resistor (approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 kΩ and 2.0 kΩ, respectively, should be
used to pull a signal to the opposite supply rail.]
§ _{PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these}
pins [C6711/11B only].
¶ _{A = Analog signal (PLL Filter)}
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