TMS320C6711 Datasheet, PDF (75/129 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS088L − FEBRUARY 1999 − REVISED MAY 2004
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles^{†‡§} (see Figure 30−Figure 31) [C6711]
NO.
3
t_su(EDV-AREH)
Setup time, EDx valid before ARE high
4
t_h(AREH-EDV)
Hold time, EDx valid after ARE high
6 t_{su(ARDY-EKOH)} Setup time, ARDY valid before ECLKOUT high
7 t_h(EKOH-ARDY) Hold time, ARDY valid after ECLKOUT high
C6711−100
MIN MAX
13
1
6
1.7
C6711−150
MIN MAX
9
1
3
1.7
UNIT
ns
ns
ns
ns
timing requirements for asynchronous memory cycles^{†‡§} (see Figure 30−Figure 31) [C6711B]
NO.
3
t_su(EDV-AREH)
Setup time, EDx valid before ARE high
4
t_h(AREH-EDV)
Hold time, EDx valid after ARE high
6 t_{su(ARDY-EKOH)} Setup time, ARDY valid before ECLKOUT high
7 t_h(EKOH-ARDY) Hold time, ARDY valid after ECLKOUT high
C6711B-100
C6711BGFNA−100
MIN MAX
13
1
6
2.5
C6711B−150
MIN MAX
9
1
3
2.5
UNIT
ns
ns
ns
ns
timing requirements for asynchronous memory cycles^{†‡§} (see Figure 30−Figure 31) [11C/11D]
GDPA-167
−200
NO.
−250 (6711D) ^UNIT
MIN MAX
3
t_su(EDV-AREH)
4
t_h(AREH-EDV)
6
t_{su(ARDY-EKOH)}
7
t_h(EKOH-ARDY)
Setup time, EDx valid before ARE high
Hold time, EDx valid after ARE high
Setup time, ARDY valid before ECLKOUT high
Hold time, ARDY valid after ECLKOUT high
6.5
ns
1
ns
3
ns
2.3
ns
† _{To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in}
the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide
enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
‡ _{RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are}
programmed via the EMIF CE space control registers.
§ _{E = ECLKOUT period in ns}
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