TMS320C6711 Datasheet, PDF (116/129 Pages) Texas Instruments – FLOATING-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS088L − FEBRUARY 1999 − REVISED MAY 2004
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1^†‡ (see Figure 54)
[C6711]
NO.
4
t_su(DRV-CKXH)
5
t_h(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
C6711-100
C6711-150
MASTER
SLAVE
MIN MAX
MIN MAX
26
2 − 6P
4
6 + 12P
UNIT
ns
ns
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1^†‡ (see Figure 54)
[C6711B]
NO.
4
t_su(DRV-CKXH)
5
t_h(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
C6711B-100
C6711B-150
C6711BGFNA-100
MASTER
SLAVE
MIN MAX
MIN MAX
26
2 − 6P
4
14 + 12P
UNIT
ns
ns
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1^†‡ (see Figure 54)
[C6711C/C6711D]
GDPA-167
−200
NO.
−250 (6711D)
MASTER
SLAVE
MIN MAX
MIN MAX
4
t_su(DRV-CKXH)
5
t_h(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
12
2 − 6P
4
5 + 12P
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.}
‡ _{For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.}
UNIT
ns
ns
116
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