PCI1520 Datasheet, PDF (83/138 Pages) Texas Instruments – PC CARD CONTROLLERS

4.31 Retry Status Register
The retry status register enables the retry timeout counters and displays the retry expiration status. The flags are set
when the PCI1520 retries a PCI or CardBus master request and the master does not return within 2¹⁵ PCI clock
cycles. The flags are cleared by writing a 1 to the bit. These bits are expected to be incorporated into the PCI
command, PCI status, and bridge control registers by the PCI SIG. Access this register only through function 0. See
Table 4−10 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Retry status
Type
RW
RW
RC
R
RC
R
RC
R
Default
1
1
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Retry status
90h (functions 0, 1)
Read-only, Read/Write, Read/Clear
C0h
Table 4−10. Retry Status Register Description
BIT
SIGNAL TYPE
FUNCTION
PCI retry timeout counter enable. Bit 7 is encoded:
7
PCIRETRY RW
0 = PCI retry counter disabled
1 = PCI retry counter enabled (default)
CardBus retry timeout counter enable. Bit 6 is encoded:
6†
CBRETRY RW
0 = CardBus retry counter disabled
1 = CardBus retry counter enabled (default)
CardBus target B retry expired. Write a 1 to clear bit 5.
5
TEXP_CBB RC
0 = Inactive (default)
1 = Retry has expired
4
RSVD
R Reserved. Bit 4 returns 0 when read.
CardBus target A retry expired. Write a 1 to clear bit 3.
3† TEXP_CBA RC
0 = Inactive (default)
1 = Retry has expired.
2
RSVD
R Reserved. Bit 2 returns 0 when read.
PCI target retry expired. Write a 1 to clear bit 1.
1
TEXP_PCI RC
0 = Inactive (default)
1 = Retry has expired.
0
RSVD
R Reserved. Bit 0 returns 0 when read.
† _{This bit is global and is accessed only through function 0.}
4−21