PCI1520 Datasheet, PDF (54/138 Pages) Texas Instruments – PC CARD CONTROLLERS

PCI1520
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
PIC
IRQ3
IRQ4
IRQ5
IRQ10
IRQ11
IRQ15
Figure 3−14. IRQ Implementation
Power-on software is responsible for programming the multifunction routing register to reflect the IRQ configuration
of a system implementing the PCI1520. The multifunction routing register is shared between the two PCI1520
functions, and only one write to function 0 or 1 is necessary to configure the MFUNC6−MFUNC0 signals. Writing to
function 0 only is recommended. See Section 4.30, Multifunction Routing Register, for details on configuring the
multifunction terminals.
The parallel ISA-type IRQ signaling from the MFUNC6−MFUNC0 terminals is compatible with the input signal
requirements of the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs.
Design constraints may demand more MFUNC6−MFUNC0 IRQ terminals than the PCI1520 makes available.
3.7.4 Using Parallel PCI Interrupts
Parallel PCI interrupts are available when exclusively in parallel PCI interrupt/parallel ISA IRQ signaling mode, and
when only IRQs are serialized with the IRQSER protocol. Both INTA and INTB can be routed to MFUNC terminals
(MFUNC0 and MFUNC1). However, interrupts of both socket functions can be routed to INTA (MFUNC0) if bit 29
(INTRTIE) is set in the system control register (PCI offset 80h, see Section 4.29).
The INTRTIE bit affects the read-only value provided through accesses to the interrupt pin register (PCI offset 3Dh,
see Section 4.24). When the INTRTIE bit is set, both functions return a value of 01h on reads from the interrupt pin
register for both parallel and serial PCI interrupts. Table 3−11 summarizes the interrupt signaling modes.
Table 3−11. Interrupt Pin Register Cross Reference
INTRTIE BIT
INTPIN
FUNCTION 0
FUNCTION 1
0
01h
02h
1
01h
01h
3.7.5 Using Serialized IRQSER Interrupts
The serialized interrupt protocol implemented in the PCI1520 uses a single terminal to communicate all interrupt
status information to the host controller. The protocol defines a serial packet consisting of a start cycle, multiple
interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The packet data
describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA, INTB, INTC, and INTD. For details on
the IRQSER protocol, refer to the document Serialized IRQ Support for PCI Systems.
3.7.6 SMI Support in the PCI1520
The PCI1520 provides a mechanism for interrupting the system when power changes have been made to the PC
Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI) scheme.
SMI interrupts are generated by the PCI1520, when enabled, after a write cycle to either the socket control register
(CB offset 10h, see Section 6.5) of the CardBus register set, or the ExCA power control register (ExCA offset
02h/42h/802h, see Section 5.3) causes a power cycle change sequence to be sent on the power switch interface.
The SMI control is programmed through three bits in the system control register (PCI offset 80h, see Section 4.29).
These bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 3−12 describes the SMI control
bits function.
3−18