PCI1520 Datasheet, PDF (127/138 Pages) Texas Instruments – PC CARD CONTROLLERS

Table 6−5. Socket Force Event Register Description
BIT
SIGNAL
TYPE
FUNCTION
31−28
RSVD
R Reserved. Bits 31−28 return 0s when read.
27 FZVSUPPORT W Zoomed-video support. This bit indicates whether or not the socket has support for zoomed video.
26−15
RSVD
R Reserved. Bits 26−15 return 0s when read.
Card VS test. When bit 14 is set, the PCI1520 re-interrogates the PC Card, updates the socket present-state
14
CVSTEST
W register (CB offset 08h, see Section 6.3), and enables the socket control register (CB offset 10h, see
Section 6.5).
Force YV card. Write transactions to bit 13 cause bit 13 (YVCARD) in the socket present-state register (CB
13
FYVCARD
W offset 08h, see Section 6.3) to be written. When set, this bit disables the socket control register (CB offset
10h, see Section 6.5).
Force XV card. Write transactions to bit 12 cause bit 12 (XVCARD) in the socket present-state register (CB
12
FXVCARD
W offset 08h, see Section 6.3) to be written. When set, this bit disables the socket control register (CB offset
10h, see Section 6.5).
Force 3-V card. Write transactions to bit 11 cause bit 11 (3VCARD) in the socket present-state register (CB
11
F3VCARD
W offset 08h, see Section 6.3) to be written. When set, this bit disables the socket control register (CB offset
10h, see Section 6.5).
Force 5-V card. Write transactions to bit 10 cause bit 10 (5VCARD) in the socket present-state register (CB
10
F5VCARD
W offset 08h, see Section 6.3) to be written. When set, this bit disables the socket control register (CB offset
10h, see Section 6.5).
9
FBADVCCREQ
W
Force bad VCC request. Changes to bit 9 (BADVCCREQ) in the socket present-state register (CB offset 08h,
see Section 6.3) can be made by writing to bit 9.
8
FDATALOST
W
Force data lost. Write transactions to bit 8 cause bit 8 (DATALOST) in the socket present-state register (CB
offset 08h, see Section 6.3) to be written.
Force not-a-card. Write transactions to bit 7 cause bit 7 (NOTACARD) in the socket present-state register
7
FNOTACARD W _{(CB offset 08h, see Section 6.3) to be written.}
6
RSVD
R Reserved. Bit 6 returns 0 when read.
5
FCBCARD
W
Force CardBus card. Write transactions to bit 5 cause bit 5 (CBCARD) in the socket present-state register
(CB offset 08h, see Section 6.3) to be written.
4
F16BITCARD
W
Force 16-bit card. Write transactions to bit 4 cause bit 4 (16BITCARD) in the socket present-state register
(CB offset 08h, see Section 6.3) to be written.
Force power cycle. Write transactions to bit 3 cause bit 3 (PWREVENT) in the socket event register (CB
3 FPWRCYCLE W offset 00h, see Section 6.1) to be written, and bit 3 (PWRCYCLE) in the socket present-state register (CB
offset 08h, see Section 6.3) is unaffected.
Force CCD2. Write transactions to bit 2 cause bit 2 (CD2EVENT) in the socket event register (CB offset 00h,
2
FCDETECT2 W see Section 6.1) to be written, and bit 2 (CDETECT2) in the socket present-state register (CB offset 08h,
see Section 6.3) is unaffected.
Force CCD1. Write transactions to bit 1 cause bit 1 (CD1EVENT) in the socket event register (CB offset 00h,
1
FCDETECT1 W see Section 6.1) to be written, and bit 1 (CDETECT1) in the socket present-state register (CB offset 08h,
see Section 6.3) is unaffected.
Force CSTSCHG. Write transactions to bit 0 cause bit 0 (CSTSEVENT) in the socket event register (CB
0
FCARDSTS
W offset 00h, see Section 6.1) to be written, and bit 0 (CARDSTS) in the socket present-state register (CB
offset 08h, see Section 6.3) is unaffected.
6−7