PCI1520 Datasheet, PDF (81/138 Pages) Texas Instruments – PC CARD CONTROLLERS

4.30 Multifunction Routing Register
The multifunction routing register is used to configure the MFUNC0−MFUNC6 terminals. These terminals may be
configured for various functions. All multifunction terminals default to the general-purpose input configuration. This
register is intended to be programmed once at power-on initialization. The default value for this register can also be
loaded through a serial bus EEPROM. See Table 4−9 for a complete description of the register contents.
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name
Multifunction routing
Type
R
R
R
R RW RW RW RW RW RW RW RW RW RW RW RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Type
Default
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Multifunction routing
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
BIT
31−28
27−24
23−20
19−16
15−12
11−8
Register:
Offset:
Type:
Default:
Multifunction routing
8Ch (functions 0, 1)
Read-only, Read/Write
0000 1000h
SIGNAL
RSVD
MFUNC6
MFUNC5
MFUNC4
MFUNC3
MFUNC2
Table 4−9. Multifunction Routing Register Description
TYPE
FUNCTION
R Bits 31−28 return 0s when read.
Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal
as follows:
RW
0000 = RSVD†
0001 = CLKRUN
0100 = IRQ4
0101 = IRQ5
1000 = IRQ8
1001 = IRQ9
1100 = IRQ12
1101 = IRQ13
0010 = IRQ2
0110 = IRQ6
1010 = IRQ10
1110 = IRQ14
0011 = IRQ3
0111 = IRQ7
1011 = IRQ11
1111 = IRQ15
Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal
as follows:
RW
0000 = GPI4†
0001 = GPO4
0100 = IRQ4
0101 = IRQ5
1000 = CAUDPWM 1100 = LEDA1
1001 = D3_STAT
1101 = LED_SKT
0010 = PCGNT
0110 = ZVSTAT 1010 = IRQ10
1110 = GPE
0011 = IRQ3
0111 = ZVSEL1 1011 = IRQ11
1111 = IRQ15
Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal
as follows:
NOTE: When the serial bus mode is implemented by pulling down the LATCH terminal, the MFUNC4 terminal
provides the SCL signaling.
RW
0000 = GPI3†
0100 = IRQ4
1000 = CAUDPWM 1100 = RI_OUT
0001 = GPO3
0101 = IRQ5
1001 = IRQ9
1101 = LED_SKT
0010 = LOCK PCI 0110 = ZVSTAT 1010 = IRQ10
1110 = GPE
0011 = IRQ3
0111 = ZVSEL1 1011 = IRQ11
1111 = D3_STAT
Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal
as follows:
RW
0000 = RSVD
0001 = IRQSER†
0100 = IRQ4
0101 = IRQ5
1000 = IRQ8
1001 = IRQ9
1100 = IRQ12
1101 = IRQ13
0010 = IRQ2
0110 = IRQ6
1010 = IRQ10
1110 = IRQ14
0011 = IRQ3
0111 = IRQ7
1011 = IRQ11
1111 = IRQ15
Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal
as follows:
RW
0000 = GPI2†
0001 = GPO2
0100 = IRQ4
0101 = IRQ5
1000 = CAUDPWM 1100 = RI_OUT
1001 = IRQ9
1101 = LEDA2
0010 = PCREQ
0110 = ZVSTAT 1010 = IRQ10
1110 = GPE
0011 = IRQ3
0111 = ZVSEL0 1011 = D3_STAT
1111 = IRQ7
4−19