PCI1520 Datasheet, PDF (33/138 Pages) Texas Instruments – PC CARD CONTROLLERS

Table 2−13. CardBus PC Card Interface System Terminals (Slots A and B)
TERMINAL
NAME
NUMBER
SLOT A†
SLOT B‡
I/O
PDV GHK PDV GHK
DESCRIPTION
CCLK
CardBus clock. CCLK provides synchronous timing for all transactions on the
CardBus interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO,
115 M14 48
P06
O
CCD2, CCD1, CVS2, and CVS1 are sampled on the rising edge of CCLK, and all
timing parameters are defined with the rising edge of this signal. CCLK operates at
the PCI bus clock frequency, but it can be stopped in the low state or slowed down
for power savings.
CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase
CCLKRUN 142 H15 74 R09 I/O in the CCLK frequency, and by the PCI1520 to indicate that the CCLK frequency is
going to be decreased.
CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and
signals to a known state. When CRST is asserted, all CardBus PC Card signals are
CRST
126 L15 58 W05 O placed in a high-impedance state, and the PCI1520 drives these signals to a valid
logic level. Assertion can be asynchronous to CCLK, but deassertion must be
synchronous to CCLK.
† _{Terminal name for slot A is preceded with A_. For example, the full name for terminals 115 and M14 is A_CCLK.}
‡ _{Terminal name for slot B is preceded with B_. For example, the full name for terminals 48 and P06 is B_CCLK.}
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