TLK1101E Datasheet, PDF (8/28 Pages) Texas Instruments – 11.3-Gbps Cable and PC Board Equalizer

TLK1101E
SLLS845A – AUGUST 2007 – REVISED OCTOBER 2007
SYMBOL
f_SCL
t_BUF
t_HDSTA
t_LOW
t_HIGH
t_SUSTA
t_HDDAT
t_SUDAT
t_R
t_F
t_SUSTO
Table 3. Two-Wire Serial Interface Timing Diagram Definitions
PARAMETER
SCL Clock frequency
Bus free time between START and STOP conditions
Hold time after repeated START condition. After this period, the first clock pulse is generated
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data HOLD time
Data setup time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
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MIN MAX UNIT
400 kHz
1.3
µs
0.6
µs
1.3
µs
0.6
µs
0.6
µs
0
µs
100
ns
300 ns
300 ns
0.6
µs
SDA
SCL
S
1-7
8
SLAVE
R/W
ADDRESS
9
ACK
1-7
8
REGISTER
ADDRESS
9
ACK
1-7
8
9
REGISTER
ACK
P
FUNCTION
Figure 5. Two-Wire Serial Interface Data Transfer
8
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