TLK1101E Datasheet, PDF (2/28 Pages) Texas Instruments – 11.3-Gbps Cable and PC Board Equalizer

TLK1101E
SLLS845A – AUGUST 2007 – REVISED OCTOBER 2007
www.ti.com
The output can be disabled using the DIS pin. The DIS and the LOS pin can be connected together to implement
a squelch function.
The de-emphasis, the output voltage swing, the input threshold voltage, the output disable, and the LOS assert
levels and ranges can alternatively be set using the two-wire serial interface through the SCL and SDA pins. The
external pin configuration is the default device setup method. The active device control method is selected
through register address 0 bit 0 (see Table 4 and Table 20). The two-wire serial interface also allows for the
control of the input bandwidth to optimize the device performance for various data rates.
The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal
swings as high as 1600mV_p-p differential.
The low-frequency cut-off is low enough to support low-frequency control signals such as SAS and SATA
out-of-band (OOB) signals.
BLOCK DIAGRAM
A simplified block diagram of the TLK1101E is shown in Figure 1. This compact, low power, 11.3-Gbps equalizer
consists of a high-speed data path with offset cancellation block combined with an analog input threshold
selection circuitry, a loss of signal detection block, a two-wire interface with a control-logic block, a bandgap
voltage reference, and a bias current generation block.
VCC
GND
DIN+
DIN-
VCC
50W 50W
Input Buffer
with
Selectable
Bandwidth
Offset
Cancellation
Equalizer
Stage
Loss of Signal
Detection
Output
Driver
VCC
Output
Buffer
50W 50W
DOUT+
DOUT-
LOS
SDA
SCL
DIS
LN0
LN1
LOSR
LOSL
SWG
VTH
DE0
DE1
SDA
SCL
DIS
LN 0
LN1
LOSR
LOSL
SWG
VTH
DE 0
DE 1
8-Bit Register Control Settings
8-Bit Register Input Threshold
4-Bit De-emphasis
2-Bit Output Swing
4-Bit + Select Input Bandwidth
7-Bit + Select LOS Assert Level
4-Bit
7-Bit Register
SEL_RATE
SEL_LOSL
2-Wire Interface &
Control Logic
Power-On
Reset
Band-Gap Voltage
Reference and
Bias Current
Generation
Figure 1. Simplified Block Diagram of the TLK1101E
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