TLK1101E Datasheet, PDF (7/28 Pages) Texas Instruments – 11.3-Gbps Cable and PC Board Equalizer

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TLK1101E
SLLS845A – AUGUST 2007 – REVISED OCTOBER 2007
TWO-WIRE SERIAL INTERFACE AND CONTROL LOGIC
FUNCTIONAL DESCRIPTION
The TLK1101E uses a two-wire serial interface for digital control. The two circuit inputs, SDA and SCL, are
driven, respectively, by the serial data and serial clock from a microcontroller, for example. Both inputs include
100kΩ pull-up resistors to VCC. For driving these inputs, an open-drain output is recommended.
The two-wire interface allows write access to the internal memory map to modify control registers and read
access to read out control and status signals. The TLK1101E is a slave device only which means that it cannot
initiate a transmission itself; it always relies on the availability of the SCL signal for the duration of the
transmission. The master device provides the clock signal as well as the START and STOP commands. The
protocol for a data transmission is as follows:
1. START command
2. 7-bit slave address (0101000) followed by an eighth bit which is the data direction bit (R/W). A zero indicates
a WRITE and a 1 indicates a READ.
3. 8-bit register address
4. 8-bit register data
5. STOP command
Regarding timing, the TLK1101E is I²C-compatible. The typical timing is shown in Figure 4 and a complete data
transfer is shown in Figure 5. Parameters for Figure 4 are defined in Table 3.
Bus Idle: Both SDA and SCL lines remain HIGH
Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH,
defines a START condition (S). Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH
defines a STOP condition (P). Each data transfer is terminated with a STOP condition; however, if the master still
wishes to communicate on the bus, it can generate a repeated START condition and address another slave
without first generating a STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and
is determined by the master device. The receiver acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. The
transmitter releases the SDA line and a device that acknowledges must pull down the SDA line during the
acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the
acknowledge clock pulse. Setup and hold times must be taken into account. When a slave-receiver does not
acknowledge the slave address, the data line must be left HIGH by the slave. The master can then generate a
STOP condition to abort the transfer. If the slave-receiver does acknowledge the slave address but some time
later in the transfer cannot receive any more data bytes, the master must abort the transfer. This is indicated by
the slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and the
master generates the STOP condition.
SDA
t_BUF
t_LOW
t_r
t_HIGH
t_f
t_HDSTA
SCL
P
S
t_HDSTA
t_HDDAT
t_SUDAT
S
t_SUSTA
Figure 4. Two-Wire Serial Interface Timing Diagram.
P
t_SUSTO
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TLK1101E
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