TLK1101E Datasheet, PDF (3/28 Pages) Texas Instruments – 11.3-Gbps Cable and PC Board Equalizer

TLK1101E
www.ti.com
SLLS845A – AUGUST 2007 – REVISED OCTOBER 2007
PACKAGE
For the TLK1101E a small footprint 4-mm × 4-mm 20-pin QFN package is used, with a lead pitch of 0.5mm. The
pin-out is shown in Figure 2.
RGP PACKAGE
(TOP VIEW)
20 19 18 17 16
GND 1
DIN+ 2
DIN– 3
GND 4
LOSL 5
TLK1101E
EP
15 VCC
14 DOUT+
13 DOUT–
12 VCC
11 LOSR
6 7 8 9 10
Figure 2. Pin-Out of the TLK1101E in a 4-mm × 4-mm 20-Pin QFN Package
PIN SYMBOL
TYPE
1, 4 GND
supply
2 DIN+
analog-in
3 DIN–
analog-in
5 LOSL analog-in
6 VTH
analog-in
7 SDA
digital-in/out
8 SCL
9 DIS
10 LOS
digital-in
digital-in
digital-out
11
12, 15
13
14
16
LOSR
VCC
DOUT–
DOUT+
SWG
digital-in
supply
CML-out
CML-out
three-state
17 LN1
18 LN0
19 DE1
20 DE0
EP EP
digital-in
digital-in
three-state
three-state
TERMINAL FUNCTIONS
DESCRIPTION
Circuit ground.
Non-inverted data input. On-chip 50Ω terminated to VCC.
Inverted data input. On-chip 50Ω terminated to VCC.
LOS threshold control. A controlling voltage on this pin adjusts the LOS assert and de-assert levels.
Input signal threshold control. A controlling voltage of 0V to 1V on this pin adjusts the input signal
threshold. Leave open for the default 0V differential threshold.
Bidirectional serial data pin for the SDA/SCL interface. Open drain. Always connect to a pull-up
resistor.
Serial clock pin for the SDA/SCL interface. Always connect to a pull-up resistor.
Disables CML output stage when set to high level. Internally pulled down.
High level indicates that the input signal amplitude is below the programmed threshold level. Open
drain. Requires an external 10kΩ pull-up resistor to VCC for proper operation.
LOS range select. Set to high level or leave open for upper range, or set to low level for lower range.
3.3V ± 10% supply voltage.
Inverted data output. On-chip 50Ω back-terminated to VCC.
Non-inverted data output. On-chip 50Ω back-terminated to VCC.
Output voltage swing control. Set to high level for high swing, set to low level for low swing, or leave
open for medium swing.
Interconnect length select. Supports two logic levels: high and low. (see Table 2)
Output signal de-emphasis control. Supports three logic levels: high, low, and open. (see Table 1)
Exposed die pad (EP) must be grounded.
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TLK1101E
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