TLK1101E Datasheet, PDF (5/28 Pages) Texas Instruments – 11.3-Gbps Cable and PC Board Equalizer

TLK1101E
www.ti.com
SLLS845A – AUGUST 2007 – REVISED OCTOBER 2007
AC ELECTRICAL CHARACTERISTICS (continued)
Typical operating condition is at V_CC = 3.3V and T_A = 25°C. Over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DIS = Low, SWG = Low, V_IN = 400mV_p-p,
No de-emphasis, No interconnect line
V_CC–0.113 V_CC–0.075 V_CC–0.056
V_CM,OUT
Data output common-mode voltage
DIS = Low, SWG = Open, V_IN = 400mV_p-p,
No de-emphasis, No interconnect line
V_CC–0.2 V_CC–0.15 V_CC–0.113
V
DIS = Low, SWG = High, V_IN = 400mV_p-p,
No de-emphasis, No interconnect line
V_CC–0.3 V_CC–0.225 V_CC–0.15
V_RIP
Differential output ripple
DE
Output de-emphasis⁽²⁾
DIS = High, 50% Transitions of K28.5 pattern at
11.3Gbps, No interconnect line, V_IN = 1600mV_p-p
K28.5 Pattern at 11.3Gbps, No interconnect line,
V_IN = 400mV_p-p, SWG = Open, Output de-emphasis off:
DE0 = Low, DE1 = Low
K28.5 Pattern at 11.3Gbps, No interconnect line,
V_IN = 400mV_p-p, SWG = Open, Maximum output
de-emphasis: DE0 = High, DE1 = High
1.5
5 mV_RMS
0
dB
7
DJ
Deterministic jitter
K28.5 Pattern at 11.3Gbps, 10-m 28-AWG Cable,
V_IN = 400mV_p-p, SWG = Open, No de-emphasis,
Maximum interconnect length setting
K28.5 Pattern at 11.3Gbps, 15-m 24-AWG Cable,
V_IN = 400mV_p-p, SWG = Open, No de-emphasis,
Maximum interconnect length setting
12
ps_p-p
12
RJ
Random jitter
K28.5 Pattern at 11.3Gbps, 10-m 28-AWG Cable,
V_IN = 400mV_p-p, SWG = Open, No de-emphasis,
Maximum interconnect length setting
K28.5 Pattern at 11.3Gbps, 15-m 24-AWG Cable,
V_IN = 400mV_p-p, SWG = Open, No de-emphasis,
Maximum interconnect length setting
1.0
ps_RMS
1.0
t_R
Output rise time
t_F
Output fall time
SDD11 Differential input return loss
20% to 80%, No interconnect line,
V_IN = 400mV_p-p, SWG = Open, No de-emphasis
20% to 80%, No interconnect line,
V_IN = 400mV_p-p, SWG = Open, No de-emphasis
0.01GHz < f < 3.9GHz
3.9GHz < f < 12.1GHz
20
28
ps
20
28
16
dB
See ⁽³⁾
SDD22 Differential output return loss
0.01GHz < f < 3.9GHz
3.9GHz < f < 12.1GHz
16
dB
See ⁽³⁾
SCD11
Input differential to common-mode
conversion
0.01GHz < f < 7.5GHz
7.5GHz < f < 12.1GHz
25
dB
20
SCC22 Common-mode output return loss
0.01GHz < f < 2.5GHz
2.5GHz < f < 12.1GHz
13
dB
7
V_AS
LOS Assert threshold voltage
K28.5 Pattern at 11.3Gbps, No interconnect,
LOSR = High, LOSL = Open
K28.5 Pattern at 11.3Gbps, No interconnect,
LOSR = High, LOSL = 1.0V
25
60
75
180
mV_p-p
V_DAS
LOS De-assert threshold voltage
K28.5 Pattern at 11.3Gbps, No interconnect,
LOSR = High, LOSL = Open
K28.5 Pattern at 11.3Gbps, No interconnect,
LOSR = High, LOSL = 1.0V
100
150
mV_p-p
300
450
T_AS/DAS
T_DIS
LOS Hysteresis
LOS Assert/de-assert time
Disable response time
Latency
20log(V_DAS / V_AS)
From DIN+/DIN– to DOUT+/DOUT–
2.5
4.5
2.5
20
150
dB
50 µs
ns
ps
(2) See Table 1 and Figure 3 for output de-emphasis settings
(3) Differential Return Loss given by SDD11, SDD22 = 19.3 + 26.66 log₁₀(f/8.25), f in GHz
Copyright © 2007, Texas Instruments Incorporated
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