CDC2509C Datasheet, PDF (8/12 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDC2509C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS620 – DECEMBER 1998
TYPICAL CHARACTERISTICS
0
–50
–100
–150
PHASE ERROR
vs
CLOCK FREQUENCY
VCC = 3.3 V
C(LY) = 30 pF
C(LF) = 0
TA = 25°C
See Note A
0
–50
–100
–150
PHASE ERROR
vs
SUPPLY VOLTAGE
fc = 100 MHz
C(LY) = 30 pF
C(LF) = 0
TA = 25°C
See Note A
–200
–200
–250
–250
–300
–350
–400
–300
–350
–400
–450
–450
–500
–500
20 40 60 80 100 120 140 160
3.1
3.2
3.3
3.4
3.5
fc – Clock Frequency – MHz
VCC – Supply Voltage – V
Figure 5
Figure 6
–200
–300
CDC2509C
STATIC PHASE ERROR
vs
CLOCK FREQUENCY
VCC = 3.3 V
C(LY) = C(LF) = 30 pF
TA = 25°C
See Notes B to D
–200
–300
CDC2509A
STATIC PHASE ERROR
vs
CLOCK FREQUENCY
VCC = 3.3 V
C(LY) = C(LF) = 30 pF
See Notes B to D
–400
–400
–500
–500
–600
–600
–700
35 45 55 65 75 85 95 105 115 125
fc – Clock Frequency – MHz
Figure 7
–700
35 45 55 65 75 85 95 105 115 125
fc – Clock Frequency – MHz
Figure 8
NOTES: A. Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω
B. Phase error measured from CLK to FBIN
C. CLY = Lumped capacitive load at Y
D. CLF = Lumped feedback capacitance at FBIN
8
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