CDC2509C Datasheet, PDF (3/12 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDC2509C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS620 – DECEMBER 1998
Terminal Functions
TERMINAL
NAME
NO.
CLK
24
FBIN
13
1G
11
2G
14
FBOUT
12
1Y (0:4) 3, 4, 5, 8, 9
2Y (0:3) 21, 20, 17, 16
AVCC
AGND
VCC
GND
23
1
2, 10, 15, 22
6, 7, 18, 19
TYPE
DESCRIPTION
Clock input. CLK provides the clock signal to be distributed by the CDC2509C clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
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have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
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FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally
zero phase error between CLK and FBIN.
Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are
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disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same
frequency as CLK.
Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are
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disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK.
O When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an
integrated 25-Ω series-damping resistor.
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the
O 1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each
output has an integrated 25-Ω series-damping resistor.
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the
O 2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each
output has an integrated 25-Ω series-damping resistor.
Power
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can
be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and
CLK is buffered directly to the device outputs.
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
Power Power supply
Ground Ground
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