CDC2509C Datasheet, PDF (5/12 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDC2509C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS620 – DECEMBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
Input clamp voltage
VOH High-level output voltage
VOL Low-level output voltage
IOH
High-level output current
IOL
Low-level output current
II
ICC§
Input current
Supply current
TEST CONDITIONS
II = –18 mA
IOH = –100 µA
IOH = –12 mA
IOH = – 6 mA
IOL = 100 µA
IOL = 12 mA
IOL = 6 mA
VO = 1 V
VO = 1.65 V
VO = 3.135 V
VO = 1.95 V
VO = 1.65 V
VO = 0.4 V
VI = VCC or GND
VI = VCC or GND,
Outputs: low or high
IO = 0,
VCC, AVCC
3V
MIN to MAX
3V
3V
MIN to MAX
3V
3V
3.135 V
3.3 V
3.465 V
3.135 V
3.3 V
3.465 V
3.6 V
MIN TYP‡
VCC–0.2
2.1
2.4
–32
–36
34
40
MAX
–1.2
0.2
0.8
0.55
–12
14
±5
UNIT
V
V
V
mA
mA
µA
3.6 V
10 µA
∆ICC Change in supply current
One input at VCC – 0.6 V,
Other inputs at VCC or GND
3.3 V to 3.6 V
500 µA
Ci
Input capacitance
VI = VCC or GND
3.3 V
4
pF
Co
Output capacitance
VO = VCC or GND
3.3 V
6
pF
‡ _{For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.}
§ _{For ICC of AVCC, and ICC vs Frequency (see Figures 11 and 12).}
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C_L = 30 pF (see Note 6 and Figures 1 and 2)^‡
PARAMETER
FROM
(INPUT)/CONDITION
TO
(OUTPUT)
VCC, AVCC = 3.3 V
± 0.165 V
MIN TYP MAX
UNIT
tsk(o)
Phase error time – static (normalized)
(See Figures 3 – 8)
Output skew time§
Phase error time – jitter (see Note 7)
Jitter(cycle-cycle)
(See Figures 9 and 10)
CLKIN↑ = 66 MHz to100 MHz
Any Y or FBOUT
Clkin = 66 MHz to 100 MHz
FBIN↑
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
–150
–50
150 ps
200 ps
50
ps
|100|
Duty cycle
F(clkin > 60 MHz)
Any Y or FBOUT 45%
55%
tr
Rise time (See Notes 8 and 9)
VO = 1.2 V to 1.8 V,
IBIS simulation
Any Y or FBOUT
2.5
1 V/ns
tf
Fall time (See Notes 8 and 9)
VO = 1.2 V to 1.8 V,
IBIS simulation
Any Y or FBOUT
2.5
1 V/ns
‡ _{These parameters are not production tested.}
§ _{The tsk(o) specification is only valid for equal loading of all outputs.}
NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
7. Calculated per PC DRAM SPEC (tphase _error, static – jitter(cycle-to-cycle)).
8. This is equivalent to 0.8 ns/2.5 ns and 0.8 ns/2.7 ns into standard 500 Ω/ 30 pf load for output swing of 04. V to 2 V.
9. 64 MB DIMM configuration according to PC SDRAM Registered DIMM Design Support Document, Figure 20 and Table 13.
Intel is a trademark of Intel Corporation.
PC SDRAM Register DIMM Design Support Document is published by Intel Corporation.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
5