CDC2509C Datasheet, PDF (7/12 Pages) Texas Instruments – 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDC2509C
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
TYPICAL CHARACTERISTICS
CDC2509C
PHASE ADJUSTMENT SLOPE AND PHASE ERROR
vs
LOAD CAPACITANCE
20
200
VCC = 3.3 V
fc = 100 MHz
10
C(LY) = 30pF
100
TA = 25°C
See Notes A and B
0
0
Phase Error
–10
–100
SCAS620 – DECEMBER 1998
–20
–200
–30
–300
Phase Adjustment Slope
–40
–400
0 5 10 15 20 25 30 35 40 45 50
C(LF) – Lumped Feedback Capacitance at FBIN – pF
Figure 3
CDC2509A
PHASE ADJUSTMENT SLOPE AND PHASE ERROR
vs
LOAD CAPACITANCE
10
100
VCC = 3.3 V
fc = 100 MHz
0
C(LY) = 30pF
0
TA = 25°C
See Notes A and B
–10
Phase Error
–100
–20
–200
–30
–300
–40
–400
Phase
Adjustment Slope
–50
–500
0 5 10 15 20 25 30 35 40 45 50
C(LF) – Lumped Feedback Capacitance at FBIN – pF
Figure 4
NOTES: A. Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω Phase error measured from CLK to Y
B. CLF = Lumped feedback capacitance at FBIN
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