TMS320DM642 Datasheet, PDF (76/178 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor
SPRS200J – JULY 2002 – REVISED AUGUST 2005
www.ti.com
The McASP0, McBSP0, McBSP1, VP0, VP1, VP2, and I2C0 peripheral functions are selected via the
peripheral configuration (PERCFG) register bits.
For more detailed information on the peripheral configuration pins and the PERCFG register bits, see the
Device Configurations section of this document.
5.3.5 Power-Down Modes Logic
Figure 5-6 shows the power-down mode logic on the DM642.
CLKOUT4 CLKOUT6
Internal Clock Tree
PD1
Clock
Distribution
and Dividers
PD2
Clock
PLL
Power-
Down
Logic
IFR
IER
PWRD ^CSR
CPU
Internal
Peripherals
PD3
TMS320DM642
CLKIN
RESET
A. External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic.
Figure 5-6. Power-Down Mode Logic^(A)
76
DM642 Peripheral Information and Electrical Specifications