TMS320DM642 Datasheet, PDF (63/178 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processor

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TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor
SPRS200J – JULY 2002 – REVISED AUGUST 2005
3.5 Multiplexed Pin Configurations
Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed.
Some of these pins are configured by software, and the others are configured by external pullup/pulldown
resistors only at reset. Those muxed pins that are configured by software should not be programmed to
switch functionalities during run-time. Those muxed pins that are configured by external pullup/pulldown
resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after
reset. Table 3-8 identifies the multiplexed pins on the DM642 device; shows the default (primary) function
and the default settings after reset; and describes the pins, registers, etc. necessary to configure specific
multiplexed functions.
Table 3-8. DM642 Device Multiplexed Pin Configurations⁽¹⁾
MULTIPLEXED PINS
NAME
NO.
CLKOUT4/GP0[1]
D6
DEFAULT
FUNCTION
CLKOUT4
DEFAULT
SETTING
GP1EN = 0 (disabled)
CLKOUT6/GP0[2]
C6 CLKOUT6
GP2EN = 0 (disabled)
DESCRIPTION
These pins are software-configurable. To use these pins
as GPIO pins, the GPxEN bits in the GPIO Enable
Register and the GPxDIR bits in the GPIO Direction
Register must be properly configured.
GPxEN = 1: GPx pin enabled
GPxDIR = 0: GPx pin is an input
GPxDIR = 1: GPx pin is an output
The VDAC output pin function is default.
VDAC/GP0[8]
AD1 VDAC
GP8EN = 0 (disabled)
MAC_EN = 0 (disabled)
To use GP0[8] as a GPIO pin, the PCI needs to be
disabled (PCI_EN = 0), the GPxEN bits in the GPIO
Enable Register and the GPxDIR bits in the GPIO Direc-
tion Register must be properly configured.
GP8EN = 1: GP8 pin enabled
GP8DIR = 0: GP8 pin is an input
GP8DIR = 1: GP8 pin is an output
GP0[9]/PIDSEL
GP0[10]/PCBE3
GP0[11]/PREQ
GP0[12]/PGNT
GP0[13]/PINTA
GP0[14]/PCLK
GP0[15]/PRST
VP1D[19]/AXR0[7]
VP1D[18]/AXR0[6]
VP1D[17]/AXR0[5]
VP1D[16]/AXR0[4]
VP1D[15]/AXR0[3]
VP1D[14]/AXR0[2]
VP1D[13]/AXR0[1]
VP1D[12]/AXR0[0]
K3
J2
F1
H4
G4
C1
G3
AB12
AB11
AC11
AD11
AE11
AC10
AD10
AC9
None
None
Note: If the PCI peripheral is disabled (PCI_EN pin = 0),
this pin must not be pulled up.
GPxEN = 0 (disabled)
PCI_EN = 0 (disabled)⁽¹⁾
To use GP0[15:9] as GPIO pins, the PCI needs to be
disabled (PCI_EN = 0), the GPxEN bits in the GPIO
Enable Register and the GPxDIR bits in the GPIO Direc-
tion Register must be properly configured.
GPxEN = 1: GPx pin enabled
GPxDIR = 0: GPx pin is an input
GPxDIR = 1: GPx pin is an output
By default, no function is enabled upon reset.
VP1EN bit = 0 (disabled)
MCASP0EN bit = 0
(disabled)
To enable the Video Port 1 data pins, the VP1EN bit in the
PERCFG register must be set to a 1. (McASP0 data pins
are disabled).
To enable the McASP0[7:0] data pins, the MCASP0EN bit
in the PERCFG register must be set to a 1. (VP1 upper
data pins are disabled).
(1) All other standalone PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled [PCI_EN = 0].
Device Configurations
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