TMS320DM642 Datasheet, PDF (154/178 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor
SPRS200J – JULY 2002 – REVISED AUGUST 2005
Table 5-70. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS RANGE
01C8 0124
01C8 0128
01C8 012C
01C8 0130
01C8 0134
01C8 0138
01C8 013C
01C8 0140
01C8 0144
01C8 0148
01C8 014C
01C8 0150
01C8 0154
01C8 0158
01C8 015C
01C8 0160
01C8 0164
01C8 0168 – 01C8 016C
01C8 0170
01C8 0174
01C8 0178
01C8 017C
01C8 0180
01C8 0184 – 01C8 018F
01C8 0190
01C8 0194
01C8 0198
01C8 019C
01C8 01A0
01C8 01A4
01C8 01A8
01C8 01AC
01C8 01B0
01C8 01B4
01C8 01B8
01C8 01BC
01C8 01C0
01C8 01C4
01C8 01C8
01C8 01CC
01C8 01D0
01C8 01D4
01C8 01D8
01C8 01DC
ACRONYM
RX1FLOWTHRESH
RX2FLOWTHRESH
RX3FLOWTHRESH
RX4FLOWTHRESH
RX5FLOWTHRESH
RX6FLOWTHRESH
RX7FLOWTHRESH
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
RX4FREEBUFFER
RX5FREEBUFFER
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
–
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
–
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
MACADDRL0
MACADDRL1
MACADDRL2
MACADDRL3
MACADDRL4
MACADDRL5
MACADDRL6
MACADDRL7
MACADDRM
MACADDRH
MACHASH1
MACHASH2
REGISTER NAME
Reserved. Do not write.
Receive Channel 0 Free Buffer Count Register
Reserved. Do not write.
MAC Control Register
MAC Status Register (RXQOSACT field is reserved.)
Reserved
Transmit Interrupt Status (Unmasked) Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Mask Clear Register
MAC Input Vector Register
Reserved
Receive Interrupt Status (Unmasked) Register
(Bits 7–1 are reserved.)
Receive Interrupt Status (Masked) Register
(Bits 7–1 are reserved.)
Receive Interrupt Mask Set Register
(Bits 7–1 are reserved and only support writes of 0.)
Receive Interrupt Mask Clear Register
(Bits 7–1 are reserved and only support writes of 0.)
MAC Interrupt Status (Unmasked) Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
MAC Address Channel 0 Lower Byte Register
Reserved. Do not write.
MAC Address Middle Byte Register
MAC Address High Bytes Register
MAC Address Hash 1 Register
MAC Address Hash 2 Register
154 DM642 Peripheral Information and Electrical Specifications
www.ti.com