TMS320DM642 Datasheet, PDF (122/178 Pages) Texas Instruments – Video/Imaging Fixed-Point Digital Signal Processor

TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor
SPRS200J – JULY 2002 – REVISED AUGUST 2005
11
SDA
8
4
10
6
5
SCL
1
12
3
7
2
3
Stop Start
Repeated
Start
Figure 5-36. I2C Receive Timings
www.ti.com
9
14
13
Stop
Table 5-37. Switching Characteristics for I2C Timings⁽¹⁾ (see Figure 5-37)
–500
–600
–720
NO.
PARAMETER
STANDARD
MODE
FAST MODE
UNIT
MIN MAX
MIN MAX
16
t_c(SCL)
Cycle time, SCL
10
17
t_d(SCLH-SDAL)
Delay time, SCL high to SDA low (for a repeated START
condition)
4.7
2.5
µs
0.6
µs
18
t_d(SDAL-SCLL)
Delay time, SDA low to SCL low (for a START and a repeated
START condition)
4
0.6
µs
19
t_w(SCLL)
Pulse duration, SCL low
4.7
20
t_w(SCLH)
Pulse duration, SCL high
4
21 t_d(SDAV-SDLH) Delay time, SDA valid to SCL high
250
22 t_v(SDLL-SDAV) Valid time, SDA valid after SCL low (For I²C bus™ devices)
0
23
t_w(SDAH)
Pulse duration, SDA high between STOP and START con-
ditions
4.7
1.3
µs
0.6
µs
100
ns
0 0.9 µs
1.3
µs
24
t_r(SDA)
Rise time, SDA
25
t_r(SCL)
Rise time, SCL
26
t_f(SDA)
Fall time, SDA
27
t_f(SCL)
Fall time, SCL
28 t_d(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition)
29 C_p
Capacitance for each I2C pin
1000 20 + 0.1C_b(1)
1000 20 + 0.1C_b(1)
300 20 + 0.1C_b(1)
300 20 + 0.1C_b(1)
4
0.6
10
300 ns
300 ns
300 ns
300 ns
µs
10 pF
(1) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
122 DM642 Peripheral Information and Electrical Specifications