TMS320LF2401A_09 Datasheet, PDF (75/88 Pages) Texas Instruments – DSP CONTROLLERS

TMS320LF2401A, TMS320LC2401A
DSP CONTROLLERS
SPRS161K − MARCH 2001 − REVISED JULY 2007
10-bit analog-to-digital converter (ADC)
The 10-bit ADC has a separate power bus for its analog circuitry. These pins are referred to as V_CCA and V_SSA.
The power bus isolation is to enhance ADC performance by preventing digital switching noise of the logic
circuitry that can be present on V_SS and V_CC from coupling into the ADC analog stage. All ADC specifications
are given with respect to V_SSA unless otherwise noted.
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-bit (1024 values)
Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assured
Output conversion mode . . . . . . . . . . . . . . . . . . . . . . . 000h to 3FFh (000h for V_I ≤ V_SSA; 3FFh for V_I ≥ V_CCA)
Conversion time (including sample time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
recommended operating conditions
MIN
NOM
VCCA†
VSSA†
Analog supply voltage
Analog ground
3.0
3.3
0
VAI
Analog input voltage, ADCIN00−ADCIN04
VREFLO
† _{VCCA and VSSA must be stable, within ±1/2 LSB of the required resolution, during the entire conversion time.}
MAX
3.6
VREFHI
UNIT
V
V
V
ADC operating frequency
ADC operating frequency
MIN MAX UNIT
2 30 MHz
operating characteristics over recommended operating condition ranges
PARAMETER
DESCRIPTION
MIN
IADCIN
Analog input leakage
Typical capacitive load on
Non-sampling
Cai
Analog input capacitance
analog input pin
Sampling
EDNL
Differential nonlinearity error
Difference between the actual step width and the
ideal value
EINL
Integral nonlinearity error
Maximum deviation from the best straight line
through the ADC transfer characteristics, excluding
the quantization error
td(PU)
Delay time, power-up to ADC
valid
Time to stabilize analog stage after power-up
Analog input source impedance needed for
ZAI
Analog input source impedance conversions to remain within specifications at min
tw(SH)
Zero-offset error
TYP MAX UNIT
1 mA
10
pF
30
±2 LSB
±2 LSB
10 ms
10 Ω
8
10 LSB
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