TMS320LF2401A_09 Datasheet, PDF (34/88 Pages) Texas Instruments – DSP CONTROLLERS

TMS320LF2401A, TMS320LC2401A
DSP CONTROLLERS
SPRS161K − MARCH 2001 − REVISED JULY 2007
internal memory
The TMS320Lx2401A device is configured with the following memory modules:
D Dual-access random-access memory (DARAM)
D Single-access random-access memory (SARAM)
D ROM (LC2401A)
D Flash (LF2401A)
D Boot ROM
dual-access RAM (DARAM)
There are 544 words × 16 bits of DARAM on the 2401A device. The 2401A DARAM allows writes to and reads
from the RAM in the same cycle. The DARAM is configured in three blocks: block 0 (B0), block 1 (B1), and
block 2 (B2). Block 1 contains 256 words and Block 2 contains 32 words, and both blocks are located only in
data memory space. Block 0 contains 256 words, and can be configured to reside in either data or program
memory space. The SETC CNF (configure B0 as program memory) and CLRC CNF (configure B0 as data
memory) instructions allow dynamic configuration of the memory maps through software.
When using on-chip RAM, the 2401A runs at full speed with no wait states. The ability of the DARAM to allow
two accesses to be performed in one cycle, coupled with the parallel nature of the 2401A architecture, enables
the device to perform three concurrent memory accesses in any given machine cycle.
single-access RAM (SARAM)
There are 512 words × 16 bits of SARAM on the Lx2401A. The PON and DON bits select SARAM (512 words)
mapping in program space, data space, or both. See Table 16 for details on the SCSR2 register and the PON
and DON bits. At reset, these bits are 11, and the on-chip SARAM is mapped in both the program and data
spaces.
ROM (LC2401A)
There are 8K words × 16 bits of ROM on the LC2401A.
Flash EEPROM (LF2401A)
Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, Flash is nonvolatile.
However, it has the advantage of “in-target” reprogrammability. The LF2401A incorporates one 8K  16-bit
Flash EEPROM module in program space. The Flash module has two sectors that can be individually protected
while erasing or programming. The sector size is partitioned as 4K/4K sectors.
Unlike most discrete Flash memory, the LF2401A Flash does not require a dedicated state machine, because
the algorithms for programming and erasing the Flash are executed by the DSP core. This enables several
advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming,
the IEEE Standard 1149.1^† (JTAG) scan port provides easy access to the on-chip RAM for downloading the
algorithms and Flash code. This Flash requires 5 V for programming (at V_CCP pin only) the array. The Flash runs
at zero wait state while the device is powered at 3.3 V.
† _{IEEE Standard 1149.1−1990, IEEE Standard Test Access Port.}
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