TMS320LF2401A_09 Datasheet, PDF (46/88 Pages) Texas Instruments – DSP CONTROLLERS

TMS320LF2401A, TMS320LC2401A
DSP CONTROLLERS
SPRS161K − MARCH 2001 − REVISED JULY 2007
external reference crystal clock option
The internal oscillator is enabled by connecting a crystal across the XTAL1/CLKIN and XTAL2 pins as shown
in Figure 18a. The crystal should be in fundamental operation and parallel resonant, with an effective series
resistance of 30 Ω−150 Ω and draws no more than 1 mW; it should be specified at a load capacitance of 20 pF.
To ensure reliable starting of the internal oscillator upon power up, a 1-M Ω resistor in parallel with the crystal
(across the XTAL1 and XTAL2 pins) is recommended. See the TMS320LF2401A, TMS320LC2401A DSP
Controller Silicon Errata (literature number SPRZ013) for more details.
external reference oscillator clock option
The internal oscillator is disabled by connecting a clock signal to XTAL1/CLKIN and leaving the XTAL2 input
pin unconnected as shown in Figure 18b.
XTAL1/CLKIN
XTAL2
XTAL1/CLKIN
XTAL2
Cb1
(see Note A)
Crystal
(a)
Cb2
External Clock Signal
(see Note A)
(Toggling 0 −3.3 V)
NC
(b)
NOTE A: TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The
resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding
the proper tank component values that will ensure start-up and stability over the entire operating range.
Figure 18. Recommended Crystal / Clock Connection
low-power modes
The 2401A has an IDLE instruction. When executed, the IDLE instruction stops the clocks to all circuits in the
CPU, but the clock output from the CPU continues to run. With this instruction, the CPU clocks can be shut down
to save power while the peripherals (clocked with CLKOUT) continue to run. The CPU exits the IDLE state if
it is reset, or, if it receives an interrupt request.
clock domains
All 2401A-based devices have two clock domains:
1. CPU clock domain − consists of the clock for most of the CPU logic
2. System clock domain − consists of the peripheral clock (which is derived from CLKOUT of the CPU) and
the clock for the interrupt logic in the CPU.
When the CPU goes into IDLE mode, the CPU clock domain is stopped while the system clock domain continues
to run. This mode is also known as IDLE1 mode. The 2401A CPU also contains support for a second IDLE mode,
IDLE2. By asserting IDLE2 to the 2401A CPU, both the CPU clock domain and the system clock domain are
stopped, allowing further power savings. A third low-power mode, HALT mode, the deepest, is possible if the
oscillator and WDCLK are also shut down when in IDLE2 mode.
Two control bits, LPM1 and LPM0, specify which of the three possible low-power modes is entered when the
IDLE instruction is executed (see Table 9). These bits are located in the System Control and Status
Register 1 (SCSR1), and they are described in the TMS320LF/LC240xA DSP Controllers Reference Guide:
System and Peripherals (literature number SPRU357).
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