TLC320AC01C Datasheet, PDF (75/90 Pages) Texas Instruments – Single-Supply Analog Interface Circuit

Appendix B
Secondary Communications
The function of the control bits DS15 and DS14 and the hardware terminals FC0 and FC1 are shown below.
Any combinational state of DS15, DS14, FC1, and FC0 not shown is ignored.
BITS
DS15 DS14
0
0
0
1
1
0
1
1
1
1
1
1
1
1
CONTROL FUNCTION OF SECONDARY COMMUNICATION
TERMINALS
FC1 FC0
Ignored
On the next falling edge of FS, the AIC receives DAC data D15 – D02 at DIN and
transmits the ADC data D15 – D00 from DOUT.
Ignored
On the next falling edge of the FS, the AIC receives DAC data D15 – D02 at DIN and
transmits the ADC data D15 – D00 from DOUT.
The phase adjustment is determined by the state of DS15 and DS14 such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A′ register. When the A′
register value is negative, FS occurs earlier.
Ignored
On the next falling edge of FS, the AIC receives DAC data D15 – D02 at DIN and
transmits the ADC data D15 – D00 from DOUT.
The phase adjustment is determined by the state of D01 and D00. On the next rising
edge of FS, the next ADC/DAC sampling time occurs earlier by the number of MCLK
periods determined by the value contained in the A′ register. When the A′ register
value is negative, FS occurs later.
0
0 On the next falling edge of FS, the AIC receives DAC data D15 – D02 at DIN and
transmits the ADC data D15 – D00 from DOUT.
0
1 On the next falling edge of the FS, the AIC receives DAC data D15 – D02 at DIN and
transmits the ADC data D15 – D00 from DOUT.
The phase adjustment is determined by the state of FC1 and FC0 such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs later by the number
of MCLK periods determined by the value contained in the A′ register. When the A′
register value is negative, FS occurs earlier.
1
0 On the next falling edge of FS, the AIC receives DAC data D15 – D02 at DIN and
transmits the ADC data D15 – D00 from DOUT.
The phase adjustment is determined by the state of FC1 and FC0 such that on the
next rising edge of FS, the next ADC/DAC sampling time occurs earlier by the number
of MCLK periods determined by the value contained in the A′ register. When the A′
register value is negative, FS occurs later.
1
1 On the next falling edge of FS, the AIC receives DAC data D15 – D02 at DIN and
transmits the ADC data D15 – D00 from DOUT.
B–1