TLC320AC01C Datasheet, PDF (26/90 Pages) Texas Instruments – Single-Supply Analog Interface Circuit

2.14.1.2 Frame-Sync Delayed (FSD), Master Mode
For the master, the frame-sync delayed output occurs 1/2 shift-clock period ahead of FS to compensate for
the time delay through the master and slave devices. The timing relationships are as follows:
1. When the FSD register data is 0, then FSD goes low on the falling edge of SCLK prior to the rising
edge of SCLK when FS goes low (see Figure 4 – 4).
2. When the FSD register data is greater than 17, then FSD goes low on a rising edge of SCLK that
is the FSD register number of SCLKs after the falling edge of FS.
Register data values from 1 to 17 should not be used.
2.14.1.3 Frame Sync (FS), Slave Mode
The frame-sync timing is generated externally, applied to FS, and controls the ADC and DAC timing (see
Subsection 2.15.4). The external frame-sync width must be a minimum of one shift clock to be recognized
and can remain low until the next data frame is required.
2.14.1.4 Frame-Sync Delayed (FSD), Slave Mode
This output is fed from the master to the first slave and the first slave FSD output to the second and so on
down the chain. The FSD timing sequence in the slave mode is as follows:
1. When the FSD register data is 0, then FSD goes low after FS goes low (see Figure 4 – 5).
2. When the FSD register data is greater than 17, FSD goes low on a rising edge of SCLK that is
the FSD register number of SCLKs after the falling edge of FS.
Data values from 1 to 17 should not be used.
2.14.2 Data Out (DOUT)
DOUT is placed in the high-impedance state on the seventeenth rising edge of SCLK (internal or external)
after the falling edge of frame sync. In the primary communication, the data word is the ADC conversion
result. In the secondary communication, the data is the register read results when requested by the
read/write (R/W) bit with the eight MSBs set to 0 (see Section 2.16). If no register read is requested, the
secondary word is all zeroes.
2.14.2.1 Data Out, Master Mode
In the master mode, DOUT is taken from the high-impedance state by the falling edge of frame sync. The
most significant data bit then appears on DOUT.
2.14.2.2 Data Out, Slave Mode
In the slave mode, DOUT is taken from the high-impedance state by the falling edge of the external frame
sync or the rising edge of the external SCLK, whichever occurs first (see Figure 4 – 7). The falling edge of
frame sync can occur ± 1/4 SCLK period around the SCLK rising edge (see Figure 4 – 3). The most
significant data bit then appears on DOUT.
2.14.3 Data In (DIN)
In the primary communication, the data word is the digital input signal to the DAC channel. In the secondary
communication, the data is the control and configuration data to set up the device for a particular function
(see Section 2.16).
2.14.4 Hardware Program Terminals (FC1 and FC0)
These inputs provide for hardware programming requests for secondary communication or phase
adjustment. These inputs work in conjunction with the control bits D01 and D00 of the primary data word
or control bits DS15 and DS14 of the secondary data word. The data on FC1 and FC0 are latched on the
rising edge of the next internally generated primary or secondary frame-sync interval. These inputs should
be tied low if not used (see Section 2.17 and Table 2–3).
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