TLC320AC01C Datasheet, PDF (47/90 Pages) Texas Instruments – Single-Supply Analog Interface Circuit

3.7 Timing Requirements and Specifications in Slave Mode and Codec
Emulation Mode
3.7.1 Recommended Input Timing Requirements for Slave Mode, V_DD = 5 V
MIN NOM
MAX
tr(MCLK)
tf(MCLK)
Master clock rise time
Master clock fall time
Master clock duty cycle
40%
5
5
60%
tw(RESET)
tsu(DIN)
th(DIN)
tsu(FL-CH)
RESET pulse duration
DIN setup time before SCLK low (see Figure 4–3)
DIN hold time after SCLK high (see Figure 4–3)
Setup time from FS low to SCLK high
1 MCLK
20
20
± SCLK/4
UNIT
ns
ns
ns
ns
ns
3.7.2
Operating Characteristics Over Recommended Range of Operating Free-Air
Temperature, V_DD = 5 V (Unless Otherwise Noted) (see Note 23)
PARAMETER
MIN TYP† MAX UNIT
tc(SCLK)
tf(SCLK)
tr(SCLK)
Shift clock cycle time (see Figure 4–3)
Shift clock fall time (see Figure 4–3)
Shift clock rise time (see Figure 4–3)
Shift clock duty cycle
125
45%
ns
18 ns
18 ns
55%
td(CH-FDL)
td(CH-FDH)
td(FL-FDL)
Delay time from SCLK high to FSD low (see Figure 4–6)
Delay time from SCLK high to FSD high
Delay time from FS low to FSD low (slave to slave)
(see Figure 4–5)
50 ns
40 ns
40 ns
td(CH-DOUT)
Delay time from SCLK high to DOUT valid
(see Figures 4–3 and 4–7)
td(CH-DOUTZ)
Delay time from SCLK↑ to DOUT in high-impedance state
(see Figure 4–8)
td(ML-EL)
Delay time from MCLK low to EOC low (see Figure 4–9)
td(ML-EH)
Delay time from MCLK low to EOC high (see Figure 4–9)
tf(EL)
EOC fall time (see Figure 4–9)
tr(EH)
EOC rise time (see Figure 4–9)
td(MH-CH)
Delay time from MCLK high to SCLK high
td(MH-CL)
Delay time from MCLK high to SCLK low
† _{All typical values are at VDD = 5 V and TA = 25°C.}
NOTE 23: All timing specifications are valid with CL = 20 pF.
40 ns
20
ns
40
ns
40
ns
13
ns
13
ns
50 ns
50 ns
3–9