TMS320C6457 Datasheet, PDF (73/238 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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4.4 Bus Priorities
TMS320C6457
Fixed-Point Digital Signal Processor
SPRS582—March 2009
On the TMS320C6457 device, bus priority is programmable for each master. The register bit fields and default
priority levels for C6457 bus masters are shown in Table 4-2.
Table 4-2 TMS320C6457 Default Bus Master Priorities
Bus Master
EDMA3TC0
EDMA3TC1
EDMA3TC2
EDMA3TC3
EDMA3TC4
EDMA3TC5
EMAC
SRIO (Data Access)
SRIO (Descriptor Access)
HPI
C64x+ Megamodule (MDMA port)
End of Table 4-2
Default Priority Level
0
0
0
0
0
0
1
0
1
2
7
Priority Control
QUEPRI.PRIQ0 (EDMA3 register)
QUEPRI.PRIQ1 (EDMA3 register)
QUEPRI.PRIQ2 (EDMA3 register)
QUEPRI.PRIQ3 (EDMA3 register)
QUEPRI.PRIQ4 (EDMA3 register)
QUEPRI.PRIQ5 (EDMA3 register)
PRI_ALLOC.EMAC
PER_SET_CNTL.CBA_TRANS_PRI (SRIO register)
PRI_ALLOC.SRIO_CPPI
PRI_ALLOC.HOST
MDMAARBE.PRI (C64x+ Megamodule Register)
The priority levels should be tuned to obtain the best system performance for a particular application. Lower values
indicate higher priorities. For some masters, the priority values are programmed at the system level by configuring
the PRI_ALLOC register. Details on the PRI_ALLOC register are shown in Table 4-3 and Table 4-4. The C64x+
megamodule, SRIO, and EDMA masters contain registers that control their own priority values.
Table 4-3 Priority Allocation Register (PRI_ALLOC)
0x0288 091C
Bit
31 30 29 28 27 26 25 24 23 22
Acronym
Reset ⁽¹⁾
Reserved
R-0000 0000 0000 0000
Bit
15 14 13 12 11 10
9
8
7
6
Acronym
Reset ⁽¹⁾
Reserved
R-0000 000
HPI
R/W-010
1 R/W = Read/Write; R = Read only; -n = value after reset
21 20 19
5
4
3
SRIO_CPPI
R/W-001
18 17 16
2
1
0
EMAC
R/W-001
Table 4-4 Priority Allocation Register (PRI_ALLOC) Field Descriptions
Bit
31:16
15:9
8:6
5:3
Acronym
Reserved
Reserved
HOST
SRIO_CPPI
2:0 EMAC
End of Table 4-4
Value
0000 0000 0000 0000
0000 000
010
001
001
Description
Reserved.
Reserved.
Priority of the HPI peripheral.
Priority of the Serial RapidIO when accessing descriptors from system memory. This priority is set
in the peripheral, itself.
Priority of the EMAC peripheral.
Copyright © 2009 Texas Instruments Incorporated
System Interconnect 73