TMS320C6457 Datasheet, PDF (136/238 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6457
Fixed-Point Digital Signal Processor
SPRS582—March 2009
www.ti.com
7.6.6.3 Reset Configuration Register
This register is used to configure the type of system resets initiated by the SRIO module or a PLL controller; i.e., a
hard reset or a soft reset. By default, both the system resets will be hard resets. The Reset Configuration register
(RSTCFG) is shown in Table 7-19 and described in Table 7-20.
Table 7-19 Reset Configuration Register (RSTCFG)
Address - 029A 00ECh
Bit
31 30
29
28 27 26 25 24 23 22 21 20 19 18 17
16
Acronym
Reset ⁽¹⁾
Reserved
R-0x2000
Bit
15 14
13
12 11 10 9 8 7 6 5 4 3 2 1
0
Acronym
Reset ⁽¹⁾
Reserved
R-0x000
PLLCTLRSTTYPE
R/W-0 ⁽²⁾
Reserved
R-0x000
SRIORSTTYPE
R/W-0x0 ⁽²⁾
1 R/W = Read/Write; R = Read only; -n = value after reset
2 Writes are conditional based on valid key. For details, see Section 7.6.6.2 ‘‘Software Reset Control Register’’.
Table 7-20 Reset Configuration Register (RSTCFG) Field Descriptions
Bit Acronym Description
31:14
Reserved Reserved.
13 PLLCTLRSTTYPE PLL controller initiates a software driven reset of type:
0 = Hard reset (default)
1 = Soft reset
12:1
Reserved Reserved.
0
SRIORSTTYPE SRIO module initiates a reset of type:
0 = Hard Reset (default)
1 = Soft Reset
End of Table 7-20
136 C64x+ Peripheral Information and Electrical Specifications
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