TMS320C6457 Datasheet, PDF (70/238 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320C6457
Fixed-Point Digital Signal Processor
SPRS582—March 2009
4.2 Data Switch Fabric Connections
www.ti.com
Figure 4-1 shows the connection between slaves and masters through the data switched central resource (SCR).
Masters are shown on the left and slaves on the right. The data SCR connects masters to slaves via 128-bit data buses
running at a SYSCLK4 frequency. SYSCLK4 is supplied by the PLL controller and is fixed at a frequency equal to the
CPU frequency divided by 3.
Figure 4-1 Data Switched Central Resource Block Diagram
EDMA3 Channel
Controller
Events
Data Bus
MASTER
128
M0
128
M1
EDMA3
128
M2
Transfer
Controllers
M3
128
128
M4
128
M5
EMAC
32
M
128
Bridge
Data SCR
128
32
M
Bridge
S0
S1
S2
128
M
Bridge
S3
M
128
Bridge
S4
S5
128-bit
M
128
32
Bridge
S
HPI
M
32
128
Bridge
128
M
Bridge
Configuration Bus
SLAVE
32
S
TCP2_A
32
S
VCP2
32
S
TCP2_B
32
S
CFG
SCR
32
S
McBSP0
32
S
McBSP1
32
S
L3 ROM
32
S
UTOPIA
Serial RapidIO _M
32
(Descriptor)
Serial
RapidIO
M
(Data)
Megamodule M
128
Bridge
S
128
S
128
S
128
M
M
128
Bridge
128
M
DDR2
S
Memory
Controller
64
S
EMIFA
S ^Megamodule
70 System Interconnect
Copyright © 2009 Texas Instruments Incorporated