TMS320C6457 Datasheet, PDF (47/238 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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Table 2-6
Terminal Functions (Part 12 of 23)
TMS320C6457
Fixed-Point Digital Signal Processor
SPRS582—March 2009
Signal Name
Ball No. Type IPD/IPU Description
UNIVERSAL TEST AND OPERATIONS PHY INTERFACE for ASYNCHRONOUS TRANSFER MODE (ATM) [UTOPIA SLAVE]
UXCLK
UTOPIA SLAVE (ATM CONTROLLER) — TRANSMIT INTERFACE
A4
I
Source clock for UTOPIA transmit driven by Master ATM Controller.
UXCLAV
C3
O/Z
Transmit cell available status output signal from UTOPIA Slave.
• 0 indicates a complete cell is NOT available for transmit
• 1 indicates a complete cell is available for transmit
UXENB
B3
I
UTOPIA transmit interface enable input signal. Asserted by the Master ATM Controller to indicate
that the UTOPIA Slave should put out on the Transmit Data Bus the first byte of valid data and
the UXSOC signal in the next clock cycle.
UXSOC
G4
O/Z
Transmit Start-of-Cell signal. This signal is output by the UTOPIA Slave on the rising edge of the
UXCLK, indicating that the first valid byte of the cell is available on the 8-bit Transmit Data Bus
(UXDATA[7:0]).
UXADDR4
J4
UXADDR3
UXADDR2
UXADDR1
H5
K3
I
J5
UTOPIA transmit address pins (UXADDR[4:0]) (I) 5-bit Slave transmit address input pins driven by
the Master ATM Controller to identify and select one of the Slave devices (up to 31 possible) in
the ATM System.
UXADDR0
H4
UXDATA7
F3
UXDATA6
E4
UXDATA5
C4
UXDATA4
UXDATA3
A3
O/Z
H3
UTOPIA 8-bit transmit data bus (I/O/Z) Using the Transmit Data Bus, the UTOPIA Slave (on the
rising edge of the UXCLK) transmits the 8-bit ATM cells to the Master ATM Controller.
UXDATA2
G3
UXDATA1
F4
UXDATA0
E3
URCLK
URCLAV
URENB
URSOC
URADDR4
URADDR3
URADDR2
URADDR1
URADDR0
UTOPIA SLAVE (ATM CONTROLLER) — RECEIVE INTERFACE
C1
I
Source clock for UTOPIA receive driven by Master ATM Controller.
B2
O/Z
Receive cell available status output signal from UTOPIA Slave.
• 0 indicates NO space is available to receive a cell from Master ATM Controller.
• 1 indicates space is available to receive a cell from Master ATM Controller.
K4
I
UTOPIA receive interface enable input signal. Asserted by the Master ATM Controller to indicate
to the UTOPIA Slave to sample the Receive Data Bus (URDATA[7:0]) and URSOC signal in the next
clock cycle or thereafter.
G2
I
Receive Start-of-Cell signal. This signal is output by the Master ATM Controller to indicate to the
UTOPIA Slave that the first valid byte of the cell is available to sample on the 8-bit Receive Data
Bus (URDATA[7:0]).
K1
K2
J1
I
J3
UTOPIA receive address pins [URADDR[4:0] (I)]: 5-bit Slave receive address input pins driven by
the Master ATM Controller to identify and select one of the Slave devices (up to 31 possible) in
the ATM System.
H2
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Device Overview 47