TMS320C6455 Datasheet, PDF (71/116 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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EVENT NUMBER
INT_114 - INT_115
INT_116
INT_117
INT_118
INT_119
INT_120
INT_121
INT_122
INT_123
INT_124
INT_125
INT_126
INT_127
TMS320C6455 Fixed-Point Digital Signal Processor
SPRS276 – MAY 2005
Table 6-3. C6455 DSP Interrupts (continued)
INTERRUPT EVENT
Reserved
L2_ED1
L2_ED2
PDC_INT
Reserved
L1P_CMPA
L1P_DMPA
L1D_CMPA
L1D_DMPA
L2_CMPA
L2_DMPA
IDMA_CMPA
IDMA_BUSERR
INTERRUPT SOURCE
Reserved. Do not use.
L2 single bit error detected
L2 two bit error detected
Powerdown sleep interrupt
Reserved. Do not use.
L1P CPU memory protection fault
L1P DMA memory protection fault
L1D CPU memory protection fault
L1D DMA memory protection fault
L2 CPU memory protection fault
L2 DMA memory protection fault
IDMA CPU memory protection fault
IDMA bus error interrupt
6.9.2 Interrupts Peripheral Register Description(s)
6.9.3 Interrupts Electrical Data/Timing
6.10 Reset
The C6455 device has several types of resets – Power-on Reset, Warm Reset, Max Reset, System
Reset, and CPU Reset. Table 6-4 explains further the types of reset, the reset initiator, and the effects on
the chip.
Table 6-4. Reset Types
TYPE
INITIATOR
EFFECT(s)
POR (power-on-reset)
Hardware circuit detects power on condition.
POR pin active low.
Resets the entire chip including reset of the test/emulation logic.
Total reset of chip (cold reset). Activates the POR signal on-chip.
Warm Reset
RESET pin active low
Resets everything exceptfor test/emulation logic. Emulator stays
alive during Warm Reset.
Max Reset
RapidIO
Emulator
Same as a Warm Reset.
System Reset
Emulator
Soft Reset. A soft reset maintains memory contents and does not
affect or reset the Device Configuration pins, the PLL1 and PLL2
peripherals, the PLL1 Controller, the PowerSaver module, or the
Test/Emulation circuitry.
CPU Reset
HPI
Resets the CPU.
6.10.1 Power-on Reset (POR Pin)
Note: The reset (RESET) pin must be held inactive (High) throughout the Power-On Reset.
1. During Power up, the power-on reset (POR) pin must be low [active].
2. Once the power supplies are within valid operating conditions, the POR pin must be held low for a
minimum of 256 CLKIN1 cycles before being pulled high. Within the minimum 256 CLKIN1 cycles, the
following happens:
C6455 Peripheral Information and Electrical Specifications
71