TMS320C6455 Datasheet, PDF (1/116 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

www.ti.com
TMS320C6455 Fixed-Point Digital Signal Processor
SPRS276 – MAY 2005
1 TMS320C6455 Fixed-Point Digital Signal Processor
1.1 Features
• High-Performance Fixed-Point DSP (C6455)
– 1.39-, 1.17-, 1-ns Instruction Cycle Time
– 720-, 850-MHz and 1-GHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 5760, 6800, 8000 MIPS
– 5760, 6800, 8000 MMACS (16 Bits)
– Commercial Temperature [0°C to 90°C]
• TMS320C64x+™ DSP Core
– Dedicated SPLOOP Instruction
– Compact Instructions (32-/16-Bit)
– Instruction Set Enhancements
– Exception Handling
• TMS320C64x+ Megamodule
• L1/L2 Memory Architecture:
– 256K-Bit (32K-Byte) L1P Program Cache
[Direct Mapped]
– 256K-Bit (32K-Byte) L1D Data Cache
[2-Way Set-Associative]
– 16M-Bit (2048K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
• Enhanced Viterbi Decoder Coprocessor (VCP2)
– Supports Over 694 7.95-Kbps AMR
– Programmable Code Parameters
• Enhanced Turbo Decoder Coprocessor (TCP2)
– Supports up to Eight 2-Mbps 3GPP
(6 Iterations)
– Programmable Turbo Code and Decoding
Parameters
• Endianess: Little Endian, Big Endian
• 64-Bit/133-MHz EMIFA
– Glueless Interface to Asynchronous
Memories (SRAM, Flash, and EPROM)
– Glueless Interface to Synchronous
Memories (SBSRAM and ZBT SRAM)
– Supports Interface to Standard Sync
Devices
– Sync or Async Interface to Custom Logic
(FPGA, CPLD, ASICs, etc.)
– 32M-Byte Total Addressable External
Memory Space (8MB per CE space)
• 32-Bit DDR2 EMIF (DDR2-500 SDRAM)
• EDMA Controller (64 Independent Channels)
• Four 1x Serial RapidIO® Links (or One 4x),
v1.2 Compliant
– 1.25-, 2.5-, 3.125-Gbps Link Rates
– Message Passing, DirectIO Support, Error
Management Extensions, and Congestion
Control
– IEEE 1149.6 Compliant I/Os
• 32-/16-Bit Host-Port Interface (HPI)
• 32-Bit/66-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.3
• One Inter-Integrated Circuit (I²C) Bus
• Two Multichannel Buffered Serial Ports
(McBSPs)
• 10/100/1000 Mb/s Ethernet MAC (EMAC)
– IEEE 802.3 Compliant
– Supports Multiple Media Independent
Interfaces
(MII, GMII, RMII, and RGMII)
– 8 Independent Transmit (TX) and
8 Independent Received (RX) Channels
• Two 64-Bit General-Purpose Timers,
Configurable as Four 32-Bit Timers
• Universal Test and Operations PHY Interface
for ATM (UTOPIA)
– UTOPIA Level 2 Slave ATM Controller
– 8-Bit Transmit and Receive Operations up
to 50 MHz per Direction
– User-Defined Cell Format up to 64 Bytes
• 16 General-Purpose I/O (GPIO) Pins
• PLL1 and PLL1 Controller
• PLL2 Dedicated for DDR2 EMIF and EMAC
• IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible
• 697-Pin Ball Grid Array (BGA) Package
(ZTZ Suffix), 0.8-mm Ball Pitch
• 0.09-µm/7-Level Cu Metal Process (CMOS)
• 3.3-, 1.8-, 1.5-, 1.2-V I/Os, 1.2-V Internal
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the forma-
tive or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.
Copyright © 2005, Texas Instruments Incorporated