TMS320C6455 Datasheet, PDF (21/116 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

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TMS320C6455 Fixed-Point Digital Signal Processor
SPRS276 – MAY 2005
SIGNAL
NAME
RESETSTAT
POR
GP[7]
GP[6]
GP[5]
GP[4]
URADDR3/PREQ/
GP[15]
URADDR2/PINTA/
GP[14]
URADDR1/PRST/
GP[13]
URADDR0/PGNT/
GP[12]
FSX1/GP[11]
FSR1/GP[10]
DX1/GP[9]
DR1/GP[8]
CLKX1/GP[3]
URADDR4/PCBE0/
GP[2]
SYSCLK3/GP[1] ⁽³⁾
CLKR1/GP[0]
PCI_EN
HINT/PFRAME
HCNTL1/PDEVSEL
HCNTL0/PSTOP
HHWIL/PCLK
HR/W/PCBE2
HAS/PPAR
HCS/PPERR
HDS1/PSERR
HDS2/PCBE1
HRDY/PIRDY
URADDR3/PREQ/
GP[15]
URADDR2/PINTA/
GP[14]
URADDR1/PRST/
GP[13]
URADDR0/PGNT/
GP[12]
Table 2-3. Terminal Functions TBD (continued)
TYPE⁽¹⁾ IPD/IPU⁽²⁾
NO.
DESCRIPTION
O
Reset Status pin. The RESETSTAT pin indicates when the device is in reset
I
Power on reset.
I/O/Z
IPD
I/O/Z
I/O/Z
IPD
General-purpose input/output (GPIO) pins (I/O/Z).
IPD
I/O/Z
IPD
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
UTOPIA received address pins or PCI peripheral pins or General-purpose
input/output (GPIO) [15:12, 2] pins (I/O/Z) [default]
PCI bus request (O/Z) or GP[15] (I/O/Z) [default]
PCI interrupt A (O/Z) or GP[14] (I/O/Z) [default]
PCI reset (I) or GP[13] (I/O/Z) [default]
IPD
PCI bus grant (I) or GP[12] (I/O/Z) [default]
PCI command/byte enable 3 (I/O/Z) or GP[2] (I/O/Z) [default]
IPD
IPD
McBSP1 pins or GP[11:8] pins (I/O/Z) [default]
McBSP1 transmit clock (I/O/Z) or GP[3] (I/O/Z) [default]
IPD
McBSP1 receive clock (I/O/Z) or GP[0] (I/O/Z) [default]
IPD
GP[1] pin (I/O/Z). SYSCLK3 is the clock output at 1/8 of the device speed (O/Z)
or this pin can be programmed as a GP[1] pin (I/O/Z) [default].
O/Z
IPD
I/O/Z
IPD
HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI)
PCI enable pin. This pin controls the selection (enable/disable) of the HPI and
I
IPD
GP[15:8], or PCI peripherals. This pin works in conjunction with the
MCBSP1_EN (AEA5 pin) to enable/disable other peripherals (for more details,
see the Device Configurations section of this data sheet).
I/O/Z
Host interrupt from DSP to host (O/Z) or PCI frame (I/O/Z)
I/O/Z
Host control - selects between control, address, or data registers (I) [default] or
PCI device select (I/O/Z)
I/O/Z
Host control - selects between control, address, or data registers (I) [default] or
PCI stop (I/O/Z)
I/O/Z
Host half-word select - first or second half-word (not necessarily high or low
order)
[For HPI16 bus width selection only] (I) [default] or PCI clock (I)
I/O/Z
Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z)
I/O/Z
Host address strobe (I) [default] or PCI parity (I/O/Z)
I/O/Z
Host chip select (I) [default] or PCI parity error (I/O/Z)
I/O/Z
Host data strobe 1 (I) [default] or PCI system error (I/O/Z)
I/O/Z
Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z)
I/O/Z
Host ready from DSP to host (O/Z) [default] or PCI initiator ready (I/O/Z)
I/O/Z
UTOPIA received address pin 3 (URADDR3) or PCI bus request (O/Z) or
GP[15] (I/O/Z) [default]
I/O/Z
UTOPIA received address pin 2 or PCI interrupt A (O/Z) or
GP[14] (I/O/Z) [default]
I/O/Z
UTOPIA received address pin 1 (URADDR1) or PCI reset (I) or
GP[13] (I/O/Z) [default]
I/O/Z
UTOPIA received address pin 0 (URADDR0) or PCI bus grant (I) or
GP[12] (I/O/Z) [default]
Device Overview
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