THS1041 Datasheet, PDF (7/37 Pages) Texas Instruments – 10-Bit, 40-MSPS ANALOG-TO-DIGITAL CONVERTER WITH PGA AND CLAMP

THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUARY 2002
electrical characteristics over recommended operating conditions, AV_DD = 3 V, DV_DD = 3 V,
f_s = 40 MSPS/50% duty cycle, MODE = AV_DD (internal reference), differential input range = 1 Vpp
and 2 Vpp, PGA = 1X, T_A = T_min to T_max (unless otherwise noted) (continued)
digital specifications
Digital Inputs
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
High-level input current
IIL
Low-level input current
Ci
Input capacitance
Digital Outputs
VOH
High-level output voltage
VOL
Low-level output voltage
High impedance output current
Clock input
All other inputs
Clock input
All other inputs
Iload = 50 µA
Iload = 50 µA
Rise/fall time
Clock Input
tc
tw(CKH)
tw(CKL)
Clock cycle
Pulse duration, clock high
Pulse duration, clock low
Clock duty cycle
td(o)
Clock to data valid, delay time
Pipeline latency
td(AP)
Aperture delay time
Aperture uncertainty (jitter)
Cload = 15 pF
timing
td(DZ)
td(DEN)
td(OEW)
td(WOE)
tw(WP)
tsu
th
PARAMETER
Output disable to Hi-Z output, delay time
Output enable to output valid, delay time
Output disable to write enable, delay time
Write disable to output enable, delay time
Write pulse duration
Input data setup time
Input data hold time
MIN NOM MAX
UNIT
0.8 × AVDD
0.8 × DVDD
V
0.2 × AVDD
V
0.2 × DVDD
1 µA
|–1| ^µA
5
pF
DVDD–0.4
3.5
V
0.4 V
±1 µA
ns
25
11.25
11.25
45%
50%
9.5
4
0.1
1
200
110
110
55%
16
ns
ns
ns
ns
Cycles
ns
ps
MIN TYP MAX UNIT
0
10 ns
0
10 ns
12
ns
12
ns
15
ns
5
ns
5
ns
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