THS1041 Datasheet, PDF (6/37 Pages) Texas Instruments – 10-Bit, 40-MSPS ANALOG-TO-DIGITAL CONVERTER WITH PGA AND CLAMP

THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUARY 2002
electrical characteristics over recommended operating conditions, AV_DD = 3 V, DV_DD = 3 V,
f_s = 40 MSPS/50% duty cycle, MODE = AV_DD (internal reference), differential input range = 1 Vpp
and 2 Vpp, PGA = 1X, T_A = T_min to T_max (unless otherwise noted) (continued)
dynamic performance (ADC and PGA)
PARAMETER
ENOB Effective number of bits
SFDR Spurious free dynamic range
THD Total harmonic distortion
SNR Signal-to-noise ratio
SINAD Signal-to-noise and distortion
BW
Full power bandwidth (–3 dB)
TEST CONDITIONS
f = 4.8 MHz, –0.5 dBFS
f = 20 MHz, –0.5 dBFS
f = 4.8 MHz, –0.5 dBFS
f = 20 MHz, –0.5 dBFS
f = 4.8 MHz, –0.5 dBFS
f = 20 MHz, –0.5 dBFS
f = 4.8 MHz, –0.5 dBFS
f = 20 MHz, –0.5 dBFS
f = 4.8 MHz, –0.5 dBFS
f = 20 MHz, –0.5 dBFS
MIN TYP MAX
8.8 9.6
9.5
60.5
72
70
– 72.5 – 61.3
– 71.6
55.7
60
57
55.6 59.7
59.6
900
UNIT
Bits
dB
dB
dB
dB
MHz
PGA
PARAMETER
Gain range (linear scale)
Gain step size (linear scale)
Gain error (deviation from ideal, all gain settings)
Number of control bits
MIN
0.5
–3%
TYP MAX UNIT
4 V/V
0.5
V/V
3%
3
Bits
clamp amplifier and clamp DAC
PARAMETER
MIN TYP MAX
UNIT
Resolution
10
Bits
DAC output range
REFB
REFT
V
DAC differential nonlinearity
–1
1
LSB
DAC integral nonlinearity
±1
LSB
Clamping analog output voltage range
0.1
AVDD– 0.1
V
Clamping analog output voltage error
– 40
40
mV
NOTE: The CLAMPOUT pin must see a load capacitance of at least 10 nF to ensure stability of the on-chip clamp buffer. When using the clamp
for dc restoration, the signal coupling capacitor should be at least 10 nF. When using the clamp buffer as a dc biasing reference,
CLAMPOUT should be decoupled to analog ground through at least a 10-nF capacitor.
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