THS1041 Datasheet, PDF (25/37 Pages) Texas Instruments – 10-Bit, 40-MSPS ANALOG-TO-DIGITAL CONVERTER WITH PGA AND CLAMP

THS1041
clamp operation (continued)
SLAS289B – OCTOBER 2001 – REVISED FEBRUARY 2002
PRINCIPLES OF OPERATION
Video at AIN
Line Sync
Black
Level
CLAMP
Figure 39. Example Waveforms for Line-Clamping to a Video Input Black Level
clamp DAC output voltage range and limits
When using the internal clamp DAC, the user must ensure that the desired dc clamp level at AIN+/– lies within
the voltage range V_REFB to V_REFT. This is because the clamp DAC voltage is constrained to lie within this range
V_REFB to V_REFT. Specifically:
VDAC + V_REFB ) (V_REFT * V_REFB) (0.006 ) 0.988 (DAC code)ń1024)
(13)
DAC codes can range from 0 to 1023. Figure 40 graphically shows the clamp DAC output voltage versus the
DAC code.
VDAC
VREFT
VREFB + 0.006(VREFT–VREFB)
VREFB
0
VREFB + 0.987(VREFT–VREFB)
1023
DAC Code
Figure 40. Clamp DAC Output Voltage Versus DAC Register Code Value
If the desired dc level at AIN+/– does not lie within the voltage range V_REFT to V_REFB, then either the CLAMPIN
pin can be used instead to provide a suitable reference voltage, or it may be possible to redesign the application
to move the AIN+/– input range into the CLAMP DAC voltage range.
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