THS1041 Datasheet, PDF (15/37 Pages) Texas Instruments – 10-Bit, 40-MSPS ANALOG-TO-DIGITAL CONVERTER WITH PGA AND CLAMP

THS1041
SLAS289B – OCTOBER 2001 – REVISED FEBRUARY 2002
PRINCIPLES OF OPERATION
functional overview
Refer to functional block diagram. A single-ended, sample rate clock is required at pin CLK for device operation.
Analog inputs AIN+ and AIN– are sampled on each rising edge of CLK in a switched capacitor sample and hold
unit, the output of which feeds a programmable gain amplifier (PGA) to the ADC core, where analog-to-digital
conversion is performed against the ADC reference voltages REFT and REFB.
Internal or external ADC reference voltage configurations are selected by connecting the MODE pin
appropriately. When MODE = AGND, the user must provide external sources at pins REFB and REFT. When
MODE = AV_DD or MODE = AV_DD/2, an internal ADC references generator (A2) is enabled, which drives the
REFT and REFB pins using the voltage at pin VREF as its input. The user can choose to drive VREF from the
internal bandgap reference, or they can disable A1 and provide their own reference voltage at pin VREF.
On the fourth rising CLK edge following the edge that sampled AIN+ and AIN–, the conversion result is output
via data pins I/O0 to I/O9. The output buffers can be disabled by pulling pin OE high, allowing the user to place
device configuration data on the data pins, which are then latched into the internal control registers by strobing
the WR pin high then low. The internal registers control the data output format (unsigned or twos complement),
the PGA gain, device powerdown, and the clamp functions.
The THS1041 offers a clamp circuit suitable for dc restoration of ac-coupled signals. The clamp voltage level
can be set using an external reference applied to the CLAMPIN pin, or it can be set to a reference level provided
by an on-chip 10-bit DAC. The CLAMPOUT pin must be connected externally to AIN+ or AIN– in applications
requiring the clamp function.
The following sections explain further:
D How signals flow from AIN+ and AIN– to the ADC core, and how the reference voltages at REFT and REFB
set the ADC input range and hence the input range at AIN+ and AIN–
D How to set the ADC references REFT and REFB using external sources or the internal ADC reference buffer
(A2) to match the device input range to the input signal
D How to set the output of the internal bandgap reference (A1) if required
D How to use the clamp and device control registers
signal processing chain (sample and hold, PGA, ADC)
Figure 25 shows the signal flow through the sample and hold unit and the PGA to the ADC core.
REFT
AIN+
AIN–
VP+
VQ+
X1 ^Sample
and
X–1 _Hold
PGA
VP–
VQ–
ADC
Core
REFB
Figure 25. Analog Input Signal Flow
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