SLVU405 Datasheet, PDF (7/14 Pages) Texas Instruments – TPS7A30-49EVM-567

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Thermal Guidelines
Ch 1 (+VOUT) Voltage Transient Response, Ch 2 Applied Current Step Transient (10mA – 150mA)
Figure 5. TPS7A4901 +VOUT Load Transient
6 Thermal Guidelines
Thermal management is a key component of design of any power converter and is especially important
when the power dissipation in the LDO is high. Use the following formula to approximate the maximum
power dissipation for the particular ambient temperature:
T_J = T_A + P_D × q_JA
(3)
where T_J is the junction temperature, T_A is the ambient temperature, P_D is the power dissipation in the
device, and q_JA is the thermal resistance from junction to ambient. All temperatures are in degrees Celsius.
The maximum silicon junction temperature, T_J, must not be allowed to exceed 150°C. The layout design
must make effective use of the copper trace and plane areas as thermal sinks. This prevents T_J from
exceeding the absolute maximum rating under all temperature conditions and voltage conditions across
the part.
The designer must carefully consider the thermal design of the PCB in the layout. It is difficult to calculate
the thermal resistance for a custom layout employing some unique copper area attached to each pin of
the IC. Table 1 repeats information from the Dissipation Ratings table of the TPS7A3001 and the
TPS7A4901 data sheets for comparison with the thermal resistance, q_JA, calculated for this EVM to show
the variation in thermal resistances for given copper areas. The high-K value is determined using a
standard JEDEC high-k (2s2p) board having a 3-inch × 30-inch dimension with 1-ounce internal power
and ground planes and 2-ounce copper traces on top and bottom of the board.
SLVU405 – August 2010
Copyright © 2010, Texas Instruments Incorporated
TPS7A30-49EVM-567
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