SLVU405 Datasheet, PDF (3/14 Pages) Texas Instruments – TPS7A30-49EVM-567

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2.4 Equipment Interconnect
Operation
2.4.1 Negative Voltage LDO, TPS7A3001, Interconnect
• Negative Input Supply Voltage: Turn off the negative input power supply after verifying that its output
voltage is greater than –35 V. Connect the negative voltage lead from the negative side of the supply
to the J1 (–VIN) connector of the EVM. Connect the ground lead from the positive side of the power
supply to J2 (GND) of the EVM.
• Connect a 0-mA to 200-mA load between the negative output, J4 (–VOUT) and the negative output
return at J5 (GND).
2.4.2 Positive Voltage LDO, TPS7A4901, Interconnect
• Positive Input Supply Voltage: Turn off the positive input power supply after verifying that its output
voltage is less than +35 V. Connect the positive voltage lead from the positive side of the supply to the
J6 (+VIN) connector of the EVM. Connect the ground lead from the negative side of the power supply
to J7 (GND) of the EVM.
• Connect a 0-mA to 150-mA load between the positive output, J9 (+VOUT), and the negative output
return at J10 (GND).
3 Operation
• Turn on the negative voltage input power supply to J1 (–VIN). For initial operation, it is recommended
that the negative input power supply be set to –18 V.
• Enable the negative output, –VOUT, as desired by connecting the J3 jumper between ON and EN.
• Vary the load and the voltage at –VIN as necessary for test purposes.
• Turn on the positive voltage input power supply to J6 (+VIN). For initial operation, it is recommended
that the positive input power supply be set to +18 V.
• Enable the positive output, +VOUT, as desired by connecting the J8 jumper between ON and EN.
• Vary the load and the voltage at +VIN as necessary for test purposes.
4 Adjustable Operation
The nominal output voltage for the typical LDO circuit employing the TPS7A3001 or the TPS7A4901 is set
by two external resistors, R1and R2, as illustrated in Figure 1. R1 and R2 can be calculated for any output
voltage using the equation shown in Equation 1 and by finding the Vref voltage found in the respective
data sheet in the Electrical Characteristics table.
V_IN
C_IN
10 mF
C_NR/SS
10 nF
IN
TPS7A3001
EN
or
TPS7A4901
NR/SS
OUT
FB
GND
C_BYP
10 nF
R₁
R₂
V_OUT
C_OUT
10 mF
Figure 1. LDO Schematic Showing the R₁ and R₂ Adjustment Resistors
R₂ = R₁ ÷ [(V_OUT/V_FB) –1] more Where V_OUT / (R₁ + R₂) ≥ 5 µA
(1)
Once the resistor values have been calculated, the new resistors can be installed appropriately in the
correct place using the printed-circuit board (PCB) and schematic diagrams of Figure 5 and Figure 8.
Suggestion: When recalculating the resistor values for a particular desired output voltage, change only the
R₂ value in order to maintain that the frequency domain zero formed by R₁ and C_BYP are in accordance
with Equation 2.
F_Z = 1/(2 × p × R₁ × C_BYP)
(2)
SLVU405 – August 2010
Copyright © 2010, Texas Instruments Incorporated
TPS7A30-49EVM-567
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